FSP Configuration
  Board "Custom User Board (Any Device)"
  R7FA6E2BB3CNE
    part_number: R7FA6E2BB3CNE
    rom_size_bytes: 262144
    ram_size_bytes: 40960
    data_flash_size_bytes: 4096
    package_style: QFN
    package_pins: 48
    
  RA6E2
    series: 6
    
  RA6E2 Family
    Enable inline BSP IRQ functions: Enabled
    Security: Exceptions: Exception Response: Non-Maskable Interrupt
    Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State
    Security: System Reset Request Accessibility: Secure State
    Security: Exceptions: Prioritize Secure Exceptions: Disabled
    Security: Cache Accessibility: Both Secure and Non-Secure State
    Security: System Reset Status Accessibility: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State
    Security: SRAM Accessibility: Standby RAM: Regions 7-0 are all Secure.
    Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State
    Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State
    Security: Uninitialized Non-Secure Application Fallback: Enable Uninitialized Non-Secure Application Fallback
    Startup C-Cache Line Size: 32 Bytes
    OFS0 register settings: Independent WDT: Start Mode: IWDT is stopped after a reset
    OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles
    OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
    OFS0 register settings: Independent WDT: Window End Position:  0% (no window end position)
    OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position)
    OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
    OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby
    OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
    OFS0 register settings: WDT: Timeout Period: 16384 cycles
    OFS0 register settings: WDT: Clock Frequency Division Ratio: 128
    OFS0 register settings: WDT: Window End Position:  0% (no window end position)
    OFS0 register settings: WDT: Window Start Position: 100% (no window start position)
    OFS0 register settings: WDT: Reset Interrupt Request: Reset
    OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode
    OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
    OFS1 register settings: Voltage Detection 0 Level: 2.80 V
    OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
    Block Protection Settings (BPS): BPS0: 
    Permanent Block Protection Settings (PBPS): PBPS0: 
    Clocks: HOCO FLL Function: Disabled
    Main Oscillator Wait Time: 8163 cycles
    ID Code Mode: Unlocked (Ignore ID)
    ID Code (32 Hex Characters): FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
    
  RA6E2 event data
  RA Common
    Main stack size (bytes): 0x400
    Heap size (bytes): 0x1000
    MCU Vcc (mV): 3300
    Parameter checking: Disabled
    Assert Failures: Return FSP_ERR_ASSERTION
    Clock Registers not Reset Values during Startup: Disabled
    Main Oscillator Populated: Populated
    PFS Protect: Enabled
    C Runtime Initialization : Enabled
    Early BSP Initialization : Disabled
    Main Oscillator Clock Source: Crystal or Resonator
    Subclock Populated: Populated
    Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode
    Subclock Stabilization Time (ms): 1000
    
  Clocks
    XTAL 20000000Hz
    HOCO 20MHz
    PLL Src: XTAL
    PLL Div /1
    PLL Mul x10.0
    Clock Src: PLL
    CLKOUT Disabled
    UCLK Disabled
    CANFDCLK Disabled
    CECCLK Disabled
    I3CCLK Disabled
    ICLK Div /1
    PCLKA Div /2
    PCLKB Div /4
    PCLKC Div /4
    PCLKD Div /2
    FCLK Div /4
    CLKOUT Div /1
    UCLK Div /5
    CANFDCLK Div /6
    CECCLK Div /1
    I3CCLK Div /1
    
  Pin Configurations
    R7FA6E2BB3CNE.pincfg -> g_bsp_pin_cfg
      AVCC0 42 SYSTEM_AVCC0 - - - - - - - - IO "Read only" - 
      AVSS0 43 SYSTEM_AVSS0 - - - - - - - - IO "Read only" - 
      P000 48 - - - - Disabled - - "ADC0: AN000; IRQ: IRQ6-DS" - None - - 
      P001 47 - - - - Disabled - - "ADC0: AN001; IRQ: IRQ7-DS" - None - - 
      P002 46 - - - - Disabled - - "ADC0: AN002; IRQ: IRQ8-DS" - None - - 
      P003 41 - - - - Disabled - - "ADC0: AN007" - None - - 
      P013 40 - - - - Disabled - - "ADC0: AN011" - None - - 
      P014 39 - - - - Disabled - - "ADC0: AN012; DAC120: DA0" - None - - 
      P015 38 - - - - Disabled - - "ADC0: AN013; DAC121: DA1; IRQ: IRQ13" - None - - 
      P100 36 SCI0_RXD0 - L None "Peripheral mode" - - "AGT0: AGTIO0; GPT5: GTIOC5B; GPT_POEGA: GTETRGA; I3C/IIC: I3C_SCL; IRQ: IRQ2; QSPI: QSPCLK; SCI0: RXD0; SPI1: MISO1; SSIE: AUDIO_CLK" - I - - 
      P101 35 SCI0_TXD0 - L None "Peripheral mode" - - "AGT0: AGTEE0; GPT5: GTIOC5A; GPT_POEGB: GTETRGB; I3C/IIC: I3C_SDA; IRQ: IRQ1; QSPI: QIO1; SCI0: TXD0; SPI1: MOSI1" - O - - 
      P102 34 - - - - Disabled - - "ADC0(Digital): ADTRG0; AGT0: AGTO0; CANFD0: CRX0; GPT2: GTIOC2B; GPT_OPS: GTOWLO; QSPI: QIO0; SCI0: SCK0; SPI1: RSPCK1; SSIE0: SSIBCK0" - None - - 
      P103 33 - - - - Disabled - - "CANFD0: CTX0; GPT2: GTIOC2A; GPT_OPS: GTOWUP; QSPI: QIO3; SCI0: CTS_RTS0; SPI1: SSLB0; SSIE0: SSIFS0; SSIE0: SSILRCK0" - None - - 
      P104 32 - - - - Disabled - - "AGT1: AGTIO1; GPT1: GTIOC1B; GPT_POEGB: GTETRGB; IRQ: IRQ1; QSPI: QIO2; SPI1: SSLB1" - None - - 
      P108 25 JTAG/SWD_SWDIO - L - "Peripheral mode" - - "GPT0: GTIOC0B; GPT_OPS: GTOULO; JTAG/SWD: SWDIO; SCI9: CTS_RTS9; SPI0: SSLA0" - IO - - 
      P109 26 - - - - Disabled - - "AGT0: AGTOA0; CANFD0: CTX0; CLKOUT: CLKOUT; GPT1: GTIOC1A; GPT_OPS: GTOVUP; SCI9: TXD9; SPI0: MOSI0; SSIE0: SSITXD0" - None - - 
      P110 27 - - - - Disabled - - "AGT0: AGTOB0; CANFD0: CRX0; GPT1: GTIOC1B; GPT_OPS: GTOVLO; IRQ: IRQ3; SCI9: RXD9; SPI0: MISO0; SSIE0: SSIRXD0" - None - - 
      P111 28 - - - - Disabled - - "GPT3: GTIOC3A; IRQ: IRQ4; SCI9: SCK9; SPI0: RSPCK0; SSIE0: SSIDATA0" - None - - 
      P112 29 - - - - Disabled - - "AGT1: AGTO1; GPT3: GTIOC3B; GPT_POEGD: GTETRGD; QSPI: QSSL; SPI0: SSLA0" - None - - 
      P200 21 - - - - Disabled - - "IRQ: NMI" - None - - 
      P201 20 - - - - Disabled - - "SYSTEM: MD" - None - - 
      P206 18 - - - - Disabled - - "CEC: CECIO; GPT5: GTIOC5B; GPT_OPS: GTIU; I3C/IIC: SDA0; IRQ: IRQ0-DS; SCI9: CTS9; SPI0: MISO0; SSIE0: SSIDATA0" - None - - 
      P207 17 - - - - Disabled - - "AGT1: AGTIO1; CAC: CACREF; GPT5: GTIOC5A; GPT_OPS: GTIW; QSPI: QSSL; SCI9: SCK9; SPI0: MOSI0; SSIE0: SSIFS0; SSIE0: SSILRCK0" - None - - 
      P212 8 - - - - Disabled - - "AGT1: AGTEE1; CGC: EXTAL; GPT0: GTIOC0B; GPT_POEGD: GTETRGD; IRQ: IRQ3; SCI0: RXD0" - None - - 
      P213 7 - - - - Disabled - - "CGC: XTAL; GPT0: GTIOC0A; GPT_POEGC: GTETRGC; IRQ: IRQ2; SCI0: TXD0; SSIE: AUDIO_CLK" - None - - 
      P300 24 JTAG/SWD_SWCLK - L - "Peripheral mode" - - "GPT0: GTIOC0A; GPT_OPS: GTOUUP; JTAG/SWD: SWCLK; SPI0: SSLA1" - IO - - 
      P301 23 - - - - Disabled - - "AGT0: AGTIO0; GPT4: GTIOC4B; GPT_OPS: GTOULO; IRQ: IRQ6; SCI9: CTS_RTS9; SPI0: SSLA0; SSIE0: SSIRXD0" - None - - 
      P302 22 - - - - Disabled - - "GPT4: GTIOC4A; GPT_OPS: GTOUUP; IRQ: IRQ5; RTC: RTCOUT; SCI0: CTS0; SCI9: SCK9; SPI0: RSPCK0; SSIE0: SSITXD0" - None - - 
      P402 1 GPIO - L None "Output mode (Initial Low)" - - "AGT0: AGTIO0; AGT1: AGTIO1; CAC: CACREF; CANFD0: CRX0; GPT: GTADSM1; IRQ: IRQ4-DS; RTC: RTCIC0; SSIE: AUDIO_CLK" - IO - - 
      P403 2 - - - - Disabled - - "AGT0: AGTIO0; AGT1: AGTIO1; GPT3: GTIOC3A; IRQ: IRQ14-DS; RTC: RTCIC1" - None - - 
      P407 12 - - - - Disabled - - "ADC0(Digital): ADTRG0; AGT0: AGTIO0; GPT: GTADSM0; GPT_OPS: GTIV; I3C/IIC: SDA0; RTC: RTCOUT; SSIE0: SSIBCK0; USB FS: USB_VBUS" - None - - 
      P408 11 GPIO - H None "Output mode (Initial High)" - - "AGT1: AGTOB1; GPT1: GTIOC1B; GPT_OPS: GTIW; I3C/IIC: SCL0; IRQ: IRQ7; SSIE: AUDIO_CLK" - IO - - 
      P409 10 GPIO - H None "Output mode (Initial High)" - - "AGT1: AGTOA1; GPT1: GTIOC1A; GPT_OPS: GTOWUP; IRQ: IRQ6" - IO - - 
      P500 37 - - - - Disabled - - "ADC0: AN016; AGT0: AGTOA0; CAC: CACREF; GPT_OPS: GTIU; QSPI: QSPCLK" - None - - 
      P814 15 - - - - Disabled - - "GPT0: GTIOC0B; GPT_POEGB: GTETRGB; SYSTEM: USB_DP" - None - - 
      P815 14 - - - - Disabled - - "GPT0: GTIOC0A; GPT_POEGC: GTETRGC; SYSTEM: USB_DM" - None - - 
      RES# 19 SYSTEM_RES# - - - - - - - - IO "Read only" - 
      VCC 30 SYSTEM_VCC - - - - - - - - IO "Read only" - 
      VCC_SOSC 9 SYSTEM_VCC_SOSC - - - - - - - - IO "Read only" - 
      VCC_USB 16 SYSTEM_VCC_USB - - - - - - - - IO "Read only" - 
      VCL0 3 SYSTEM_VCL0 - - - - - - - - IO "Read only" - 
      VREFH0 45 SYSTEM_VREFH0 - - - - - - - - IO "Read only" - 
      VREFL0 44 SYSTEM_VREFL0 - - - - - - - - IO "Read only" - 
      VSS 31 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS 6 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS_USB 13 SYSTEM_VSS_USB - - - - - - - - IO "Read only" - 
      XCIN 4 CGC_XCIN - - - - - - - - IO "Read only" - 
      XCOUT 5 CGC_XCOUT - - - - - - - - IO "Read only" - 
    
  User Events
    
  User Event Links
    
  Linker Section Mappings
    
  Module "I/O Port (r_ioport)"
    Parameter Checking: Default (BSP)
    
  Module "UART (r_sci_uart)"
    Parameter Checking: Default (BSP)
    FIFO Support: Disable
    DTC Support: Disable
    Flow Control Support: Disable
    RS-485 Support: Disable
    IrDA Support: Disabled
    
  HAL
    Instance "g_ioport I/O Port (r_ioport)"
      Name: g_ioport
      1st Port ELC Trigger Source: Disabled
      2nd Port ELC Trigger Source: Disabled
      3rd Port ELC Trigger Source: Disabled
      4th Port ELC Trigger Source: Disabled
      Pin Configuration Name: g_bsp_pin_cfg
      
    Instance "g_uart0 UART (r_sci_uart)"
      General: Name: g_uart0
      General: Channel: 0
      General: Data Bits: 8bits
      General: Parity: None
      General: Stop Bits: 1bit
      Baud: Baud Rate: 115200
      Baud: Baud Rate Modulation: Disabled
      Baud: Max Error (%): 5
      Flow Control: CTS/RTS Selection: Hardware RTS
      Flow Control: Software RTS Port: Disabled
      Flow Control: Software RTS Pin: Disabled
      Extra: Clock Source: Internal Clock
      Extra: Start bit detection: Falling Edge
      Extra: Noise Filter: Disable
      Extra: Receive FIFO Trigger Level: Max
      Extra: IrDA: Enable: Disabled
      Extra: IrDA: RXD Polarity Switching: Normal
      Extra: IrDA: TXD Polarity Switching: Normal
      Extra: RS-485: DE Pin: Disable
      Extra: RS-485: DE Pin Polarity: Active High
      Extra: RS-485: DE Port Number: Disabled
      Extra: RS-485: DE Pin Number: Disabled
      Interrupts: Callback: uart0_callback
      Interrupts: Receive Interrupt Priority: Priority 12
      Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
      Interrupts: Transmit End Interrupt Priority: Priority 12
      Interrupts: Error Interrupt Priority: Priority 12
      
