/* generated vector source file - do not edit */
        #include "bsp_api.h"
        /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
        #if VECTOR_DATA_IRQ_COUNT > 0
        BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_NUM_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
        {
                        [0] = sci_uart_rxi_isr, /* SCI9 RXI (Receive data full) */
            [1] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */
            [2] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */
            [3] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */
            [4] = adc_scan_end_isr, /* ADC0 SCAN END (End of A/D scanning operation) */
            [5] = gpt_counter_overflow_isr, /* GPT0 COUNTER OVERFLOW (Overflow) */
            [6] = gpt_counter_overflow_isr, /* GPT5 COUNTER OVERFLOW (Overflow) */
            [7] = gpt_capture_compare_a_isr, /* GPT5 CAPTURE COMPARE A (Capture/Compare match A) */
            [8] = gpt_capture_compare_b_isr, /* GPT5 CAPTURE COMPARE B (Capture/Compare match B) */
            [9] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */
            [10] = usbfs_interrupt_handler, /* USBFS INT (USBFS interrupt) */
            [11] = usbfs_resume_handler, /* USBFS RESUME (USBFS resume interrupt) */
            [12] = usbfs_d0fifo_handler, /* USBFS FIFO 0 (DMA/DTC transfer request 0) */
            [13] = usbfs_d1fifo_handler, /* USBFS FIFO 1 (DMA/DTC transfer request 1) */
            [14] = fcu_frdyi_isr, /* FCU FRDYI (Flash ready interrupt) */
            [15] = fcu_fiferr_isr, /* FCU FIFERR (Flash access error interrupt) */
        };
        #if BSP_FEATURE_ICU_HAS_IELSR
        const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_NUM_ENTRIES] =
        {
            [0] = BSP_PRV_VECT_ENUM(EVENT_SCI9_RXI,GROUP0), /* SCI9 RXI (Receive data full) */
            [1] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TXI,GROUP1), /* SCI9 TXI (Transmit data empty) */
            [2] = BSP_PRV_VECT_ENUM(EVENT_SCI9_TEI,GROUP2), /* SCI9 TEI (Transmit end) */
            [3] = BSP_PRV_VECT_ENUM(EVENT_SCI9_ERI,GROUP3), /* SCI9 ERI (Receive error) */
            [4] = BSP_PRV_VECT_ENUM(EVENT_ADC0_SCAN_END,GROUP4), /* ADC0 SCAN END (End of A/D scanning operation) */
            [5] = BSP_PRV_VECT_ENUM(EVENT_GPT0_COUNTER_OVERFLOW,GROUP5), /* GPT0 COUNTER OVERFLOW (Overflow) */
            [6] = BSP_PRV_VECT_ENUM(EVENT_GPT5_COUNTER_OVERFLOW,GROUP6), /* GPT5 COUNTER OVERFLOW (Overflow) */
            [7] = BSP_PRV_VECT_ENUM(EVENT_GPT5_CAPTURE_COMPARE_A,GROUP7), /* GPT5 CAPTURE COMPARE A (Capture/Compare match A) */
            [8] = BSP_PRV_VECT_ENUM(EVENT_GPT5_CAPTURE_COMPARE_B,GROUP0), /* GPT5 CAPTURE COMPARE B (Capture/Compare match B) */
            [9] = BSP_PRV_VECT_ENUM(EVENT_ICU_IRQ4,GROUP1), /* ICU IRQ4 (External pin interrupt 4) */
            [10] = BSP_PRV_VECT_ENUM(EVENT_USBFS_INT,GROUP2), /* USBFS INT (USBFS interrupt) */
            [11] = BSP_PRV_VECT_ENUM(EVENT_USBFS_RESUME,GROUP3), /* USBFS RESUME (USBFS resume interrupt) */
            [12] = BSP_PRV_VECT_ENUM(EVENT_USBFS_FIFO_0,GROUP4), /* USBFS FIFO 0 (DMA/DTC transfer request 0) */
            [13] = BSP_PRV_VECT_ENUM(EVENT_USBFS_FIFO_1,GROUP5), /* USBFS FIFO 1 (DMA/DTC transfer request 1) */
            [14] = BSP_PRV_VECT_ENUM(EVENT_FCU_FRDYI,GROUP6), /* FCU FRDYI (Flash ready interrupt) */
            [15] = BSP_PRV_VECT_ENUM(EVENT_FCU_FIFERR,GROUP7), /* FCU FIFERR (Flash access error interrupt) */
        };
        #endif
        #endif