FSP Configuration
  Board "Custom User Board (Any Device)"
  R7FA4L1BD4CFP
    part_number: R7FA4L1BD4CFP
    rom_size_bytes: 524288
    ram_size_bytes: 65536
    data_flash_size_bytes: 8192
    package_style: LQFP
    package_pins: 100
    number of cores: 1
    
  R7FA4L1BD4CFP
  RA4L1
    series: 4
    
  RA4L1 Family
    Security: Exceptions: Exception Response: Non-Maskable Interrupt
    Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State
    Security: System Reset Request Accessibility: Secure State
    Security: Exceptions: Prioritize Secure Exceptions: Disabled
    Security: Cache Accessibility: Both Secure and Non-Secure State
    Security: System Reset Status Accessibility: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State
    Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State
    Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State
    Security: Uninitialized Non-Secure Application Fallback: Enable Uninitialized Non-Secure Application Fallback
    Startup C-Cache Line Size: 32 Bytes
    Clocks: HOCO FLL Function: Disabled
    Main Oscillator Wait Time: 262144 cycles
    
  RA4L1 Device Options
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Enabled
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Start Mode: IWDT is stopped after a reset
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Timeout Period: 2048 cycles
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Window End Position:  0% (no window end position)
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Window Start Position: 100% (no window start position)
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: Independent WDT: Stop Control: Stop counting when in Sleep,Snooze modec, or Software Standby
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Timeout Period: 16384 cycles
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Clock Frequency Division Ratio: 128
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Window End Position:  0% (no window end position)
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Window Start Position: 100% (no window start position)
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Reset Interrupt Request: Reset
    OFS Registers: OFS0 (Option Function Select Register 0) Settings: WDT: Stop Control: Stop counting when entering Sleep mode
    OFS Registers: DUALSEL (Dual Mode Select Register) Settings: Disabled
    OFS Registers: DUALSEL (Dual Mode Select Register) Settings: Bank Mode: Linear
    OFS Registers: OFS1 (Option Function Select Register 1) Settings: Disabled
    OFS Registers: OFS1 (Option Function Select Register 1) Settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
    OFS Registers: OFS1 (Option Function Select Register 1) Settings: Voltage Detection 0 Level: 1.90 V
    OFS Registers: OFS1 (Option Function Select Register 1) Settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
    OFS Registers: BANKSEL (Banksel Security Attribution) Settings: Disabled
    OFS Registers: BANKSEL (Banksel Security Attribution) Settings: Startup Bank Switch: Disabled
    OFS Registers: BANKSEL (Banksel Security Attribution) Settings: Block Swap Select: Disabled
    OFS Registers: BPS (Block Protect Setting Register) Settings: Disabled
    OFS Registers: BPS (Block Protect Setting Register) Settings: BPS0: 
    OFS Registers: BPS (Block Protect Setting Register) Settings: BPS2: 
    OFS Registers: PBPS (Permanent Block Protect Setting Register) Settings: Disabled
    OFS Registers: PBPS (Permanent Block Protect Setting Register) Settings: PBPS0: 
    OFS Registers: PBPS (Permanent Block Protect Setting Register) Settings: PBPS2: 
    OFS Registers: OFS1_SEC (Option Function Select Register 1 Secure) Settings: Enabled
    OFS Registers: OFS1_SEC (Option Function Select Register 1 Secure) Settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
    OFS Registers: OFS1_SEC (Option Function Select Register 1 Secure) Settings: Voltage Detection 0 Level: 1.90 V
    OFS Registers: OFS1_SEC (Option Function Select Register 1 Secure) Settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
    OFS Registers: BANKSEL_SEC (Bank Select Register Secure) Settings: Disabled
    OFS Registers: BANKSEL_SEC (Bank Select Register Secure) Settings: Startup Bank Switch: Disabled
    OFS Registers: BANKSEL_SEC (Bank Select Register Secure) Settings: Block Swap Select: Disabled
    OFS Registers: BPS_SEC (Block Protect Setting Register Secure) Settings: Disabled
    OFS Registers: BPS_SEC (Block Protect Setting Register Secure) Settings: BPS_SEC0: 
    OFS Registers: BPS_SEC (Block Protect Setting Register Secure) Settings: BPS_SEC2: 
    OFS Registers: PBPS_SEC (Permanent Block Protect Setting Register Secure) Settings: Disabled
    OFS Registers: PBPS_SEC (Permanent Block Protect Setting Register Secure) Settings: PBPS_SEC0: 
    OFS Registers: PBPS_SEC (Permanent Block Protect Setting Register Secure) Settings: PBPS_SEC2: 
    OFS Registers: OFS1_SEL (OFS1 Security Attribution) Settings: Enabled
    OFS Registers: OFS1_SEL (OFS1 Security Attribution) Settings: Voltage Detection 0 Level Security Attribution: VDSEL setting loads from OFS1_SEC
    OFS Registers: OFS1_SEL (OFS1 Security Attribution) Settings: Voltage Detection 0 Circuit Start Security Attribution: LVDAS setting loads from OFS1_SEC
    OFS Registers: BANKSEL_SEL (Banksel Security Attribution) Settings: Disabled
    OFS Registers: BANKSEL_SEL (Banksel Security Attribution) Settings: Flash Bank Select Accessibility: Non-Secure State
    OFS Registers: BPS_SEL (BPS Security Attribution) Settings: Disabled
    OFS Registers: BPS_SEL (BPS Security Attribution) Settings: BPS_SEL0: 
    OFS Registers: BPS_SEL (BPS Security Attribution) Settings: BPS_SEL2: 
    
  RA4L1 event data
  RA Common
    Main stack size (bytes): 0x400
    Heap size (bytes): 0x2000
    Bootloader Secondary XIP: Disabled
    MCU Vcc (mV): 3300
    Parameter checking: Disabled
    Assert Failures: Return FSP_ERR_ASSERTION
    Clock Registers not Reset Values during Startup: Disabled
    Main Oscillator Populated: Populated
    PFS Protect: Enabled
    C Runtime Initialization : Enabled
    Early BSP Initialization : Disabled
    Main Oscillator Clock Source: Crystal or Resonator
    Subclock Populated: Populated
    Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode
    Subclock Stabilization Time (ms): 1000
    
  Clocks
    XTAL 8000000Hz
    HOCO 48MHz
    PLL Src: XTAL
    PLL Div /1
    PLL Mul x8.0
    Clock Src: PLL
    CLKOUT Disabled
    CANFDCLK Disabled
    I3CCLK Disabled
    UTASEL Src: Disabled
    USBCLK Disabled
    ICLK Div /2
    PCLKA Div /2
    PCLKB Div /4
    PCLKC Div /4
    PCLKD Div /2
    FCLK Div /4
    CLKOUT Div /1
    CANFDCLK Div /8
    I3CCLK Div /1
    UARTA0 Src: UTASEL
    UARTA1 Src: UTASEL
    
  Pin Configurations
    R7FA4L1BD4CFP.pincfg -> g_bsp_pin_cfg
      AVCC0 92 SYSTEM_AVCC0 - - - - - - - - IO "Read only" - 
      AVSS0 93 SYSTEM_AVSS0 - - - - - - - - IO "Read only" - 
      P000 100 - - - - Disabled - - "ADC0: AN005; IRQ: IRQ6" - None - - 
      P001 99 - - - - Disabled - - "ADC0: AN006; IRQ: IRQ7" - None - - 
      P002 98 - - - - Disabled - - "ADC0: AN000; IRQ: IRQ8" - None - - 
      P003 97 - - - - Disabled - - "ADC0: AN001" - None - - 
      P004 96 - - - - Disabled - - "ADC0: AN002; DAC120: DA0; IRQ: IRQ9" - None - - 
      P010 95 - - - - Disabled - - "ADC0: AN003; IRQ: IRQ10; SYSTEM: VREFH0" - None - - 
      P011 94 - - - - Disabled - - "ADC0: AN004; IRQ: IRQ11; SYSTEM: VREFL0" - None - - 
      P100 75 - - - - Disabled - - "ACMPLP0: CMPIN0; AGT0: AGTIO0; CTSU: TS3; GPT5: GTIOC5B; GPT_POEGA: GTETRGA; IIC0: SDA0; IRQ: IRQ2; QSPI: QIO1; SCI0: RXD0; SLCDC: SEG45" - None - - 
      P101 74 - - - - Disabled - - "ACMPLP0: CMPREF0; AGT0: AGTEE0; CTSU: TS2; GPT5: GTIOC5A; GPT_POEGB: GTETRGB; IIC0: SCL0; IRQ: IRQ1; QSPI: QIO0; SCI0: TXD0; SLCDC: SEG44" - None - - 
      P102 73 - - - - Disabled - - "ACMPLP1: CMPIN1; ADC0(Digital): ADTRG0; AGT0: AGTO0; CANFD0: CTX0; CTSU: TS1; GPT_OPS: GTOWLO; QSPI: QIO3; SCI0: SCK0; SCI3: RXD3; SLCDC: SEG43" - None - - 
      P103 72 - - - - Disabled - - "ACMPLP1: CMPREF1; CANFD0: CRX0; CTSU: TS0; GPT_OPS: GTOWUP; QSPI: QIO2; SCI0: CTS_RTS0; SCI3: TXD3; SLCDC: SEG42" - None - - 
      P104 71 SLCDC_SEG41 - - None "Peripheral mode" - - "GPT1: GTIOC1B; GPT_POEGB: GTETRGB; IRQ: IRQ1; QSPI: QSPCLK; SCI3: SCK3; SLCDC: SEG41" - O - - 
      P105 70 SLCDC_SEG40 - - None "Peripheral mode" - - "GPT1: GTIOC1A; GPT_POEGA: GTETRGA; IRQ: IRQ0; SCI3: CTS_RTS3; SLCDC: SEG40" - O - - 
      P106 69 SLCDC_SEG39 - - - "Peripheral mode" - - "AGT0: AGTOB0; GPT_POEGD: GTETRGD; SCI3: CTS3; SLCDC: SEG39" - O - - 
      P107 68 - - - - Disabled - - "AGT0: AGTOA0; SLCDC: SEG38" - None - - 
      P108 51 JTAG/SWD_SWDIO - - - "Peripheral mode" - - "GPT0: GTIOC0B; GPT_OPS: GTOULO; JTAG/SWD: SWDIO; SCI9: CTS_RTS9; SLCDC: SEG28; SPI0: SSLA0" - IO - - 
      P109 52 SCI9_TXD9 - - - "Peripheral mode" - - "CLKOUT: CLKOUT; GPT1: GTIOC1A; GPT_OPS: GTOVUP; SCI9: TXD9; SLCDC: COM4; SLCDC: SEG0; SPI0: MOSI0" - O - - 
      P110 53 SCI9_RXD9 - - None "Peripheral mode" - - "GPT1: GTIOC1B; GPT_OPS: GTOVLO; IRQ: IRQ3; SCI9: RXD9; SLCDC: COM5; SLCDC: SEG1; SPI0: MISO0" - I - - 
      P111 54 SLCDC_SEG2 - - None "Peripheral mode" - - "CMPOUT: VCOUT; IRQ: IRQ4; SCI9: SCK9; SLCDC: COM6; SLCDC: SEG2; SPI0: RSPCK0" - O - - 
      P112 55 SLCDC_SEG3 - - - "Peripheral mode" - - "QSPI: QSSL; SCI9: CTS_RTS9; SLCDC: COM7; SLCDC: SEG3; SPI0: SSLA0" - O - - 
      P113 56 SLCDC_SEG29 - - - "Peripheral mode" - - "SLCDC: SEG29; SSIE0: SSIBCK0" - O - - 
      P114 57 SLCDC_SEG30 - - - "Peripheral mode" - - "SCI9: CTS9; SLCDC: SEG30; SSIE0: SSIFS0; SSIE0: SSILRCK0" - O - - 
      P115 58 - - - - Disabled - - "GPT4: GTIOC4A; SCI1: TXD1; SLCDC: SEG31; SSIE0: SSIRXD0" - None - - 
      P200 40 - - - - Disabled - - "IRQ: NMI" - None - - 
      P201 39 - - - - Disabled - - "SYSTEM: MD" - None - - 
      P204 33 SPI0_SSLA0 - - - "Peripheral mode" - - "GPT_OPS: GTIU; QSPI: QSPCLK; SCI4: CTS_RTS4; SLCDC: SEG18; SPI0: SSLA0" - IO - - 
      P205 32 SLCDC_COM0 - - None "Peripheral mode" - - "AGT1: AGTO1; CLKOUT: CLKOUT; GPT4: GTIOC4A; GPT_OPS: GTIV; IRQ: IRQ1; SCI4: SCK4; SLCDC: COM0; USB FS: USB_OVRCURA" - O - - 
      P206 31 SLCDC_CAPL - - None "Peripheral mode" - - "GPT3: GTIOC3B; GPT_OPS: GTIU; IRQ: IRQ0; SCI4: RXD4; SLCDC: CAPL; USB FS: USB_VBUSEN" - O - - 
      P207 30 SLCDC_CAPH - - - "Peripheral mode" - - "GPT3: GTIOC3A; QSPI: QSSL; SCI4: TXD4; SLCDC: CAPH; USB FS: USB_OVRCURB" - O - - 
      P208 37 SLCDC_COM1 - - None "Peripheral mode" - - "GPT_OPS: GTOVLO; IRQ: IRQ12; QSPI: QIO3; SLCDC: COM1" - O - - 
      P209 36 SPI0_RSPCK0 - - - "Peripheral mode" - - "GPT_OPS: GTOVUP; QSPI: QIO2; SLCDC: SEG21; SPI0: RSPCK0" - IO - - 
      P210 35 - - - - Disabled - - "GPT_OPS: GTIW; QSPI: QIO1; SLCDC: SEG20; SPI0: MISO0" - None - - 
      P211 34 SPI0_MOSI0 - - - "Peripheral mode" - - "GPT_OPS: GTIV; QSPI: QIO0; SLCDC: SEG19; SPI0: MOSI0" - IO - - 
      P212 14 - - - - Disabled - - "AGT1: AGTEE1; CGC: EXTAL; GPT0: GTIOC0B; GPT_POEGD: GTETRGD; IRQ: IRQ3; SCI0: RXD0" - None - - 
      P213 13 - - - - Disabled - - "CGC: XTAL; GPT0: GTIOC0A; GPT_POEGC: GTETRGC; IRQ: IRQ2; SCI0: TXD0" - None - - 
      P214 11 - - - - Disabled - - "CGC: XCOUT" - None - - 
      P215 10 - - - - Disabled - - "CGC: XCIN" - None - - 
      P300 50 JTAG/SWD_SWCLK - - - "Peripheral mode" - - "GPT0: GTIOC0A; GPT_OPS: GTOUUP; JTAG/SWD: SWCLK; SCI5: CTS5; SLCDC: SEG27; SPI0: SSLA1" - IO - - 
      P301 49 - - - - Disabled - - "AGT0: AGTIO0; GPT4: GTIOC4B; GPT_OPS: GTOULO; IIC0: SDA0; IRQ: IRQ6; SCI5: RXD5; SLCDC: SEG26; SPI0: SSLA2" - None - - 
      P302 48 - - - - Disabled - - "ADC0(Digital): ADTRG0; GPT4: GTIOC4A; GPT_OPS: GTOUUP; IIC0: SCL0; IRQ: IRQ5; SCI5: TXD5; SLCDC: SEG25; SPI0: SSLA3" - None - - 
      P303 47 SLCDC_COM3 - - - "Peripheral mode" - - "GPT3: GTIOC3B; SCI5: SCK5; SLCDC: COM3" - O - - 
      P304 44 SLCDC_COM2 - - None "Peripheral mode" - - "GPT3: GTIOC3A; GPT_OPS: GTOWLO; IRQ: IRQ9; SCI5: CTS_RTS5; SLCDC: COM2; UARTA0: CLKA0" - O - - 
      P305 43 SLCDC_SEG24 - - None "Peripheral mode" - - "GPT_OPS: GTOWUP; IRQ: IRQ8; SLCDC: SEG24; UARTA0: RxDA0" - O - - 
      P306 42 SLCDC_SEG23 - - - "Peripheral mode" - - "GPT_OPS: GTOULO; SLCDC: SEG23; UARTA0: TxDA0" - O - - 
      P307 41 SLCDC_SEG22 - - - "Peripheral mode" - - "GPT_OPS: GTOUUP; SLCDC: SEG22" - O - - 
      P400 1 - - - - Disabled - - "AGT1: AGTIO1; GPT2: GTIOC2A; GPT_POEGB: GTETRGB; I3C0: I3C_SCL0; IRQ: IRQ0; SCI1: TXD1; SLCDC: SEG4; SSIE: AUDIO_CLK" - None - - 
      P401 2 - - - - Disabled - - "CANFD0: CRX0; GPT2: GTIOC2B; GPT_POEGA: GTETRGA; I3C0: I3C_SDA0; IRQ: IRQ5; SCI1: RXD1; SLCDC: SEG5" - None - - 
      P402 3 GPIO - - - "Output mode (Initial Low)" - - "AGT0: AGTIO0; AGT1: AGTIO1; CAC: CACREF; CANFD0: CTX0; GPT_POEGC: GTETRGC; IRQ: IRQ4; RTC0: RTCIC0; SCI1: CTS_RTS1; SLCDC: SEG6; SSIE: AUDIO_CLK" RST IO - - 
      P403 4 GPIO - - - "Output mode (Initial Low)" - - "AGT0: AGTIO0; AGT1: AGTIO1; IRQ: IRQ14; RTC1: RTCIC1; SCI1: SCK1; SLCDC: SEG7; SSIE0: SSIBCK0" DC IO - - 
      P404 5 - - - - Disabled - - "AGT0: AGTIO0; AGT1: AGTIO1; IRQ: IRQ15; RTC2: RTCIC2; SLCDC: SEG8; SSIE0: SSIFS0; SSIE0: SSILRCK0" - None - - 
      P405 6 - - - - Disabled - - "GPT1: GTIOC1A; SLCDC: SEG9; SSIE0: SSITXD0" - None - - 
      P406 7 - - - - Disabled - - "GPT1: GTIOC1B; SLCDC: SEG10; SSIE0: SSIRXD0" - None - - 
      P407 25 - - - - Disabled - - "ADC0(Digital): ADTRG0; AGT0: AGTIO0; GPT2: GTIOC2A; RTC: RTCOUT; SCI4: CTS4; SLCDC: SEG17; USB FS: USB_VBUS" - None - - 
      P408 24 SLCDC_VL3 - - None "Peripheral mode" - - "GPT2: GTIOC2B; GPT_OPS: GTOWLO; IRQ: IRQ7; RTC0: RTCIC0; SCI3: RXD3; SCI4: CTS_RTS4; SLCDC: VL3; USB FS: USB_ID" - IO - - 
      P409 23 SLCDC_VL4 - - None "Peripheral mode" - - "GPT_OPS: GTOWUP; IRQ: IRQ6; SCI3: TXD3; SLCDC: VL4; USB FS: USB_EXICEN" - IO - - 
      P410 22 SLCDC_VL2 - - None "Peripheral mode" - - "AGT1: AGTOB1; GPT_OPS: GTOVLO; IRQ: IRQ5; SCI3: SCK3; SLCDC: VL2" - IO - - 
      P411 21 SLCDC_VL1 - - None "Peripheral mode" - - "AGT1: AGTOA1; GPT_OPS: GTOVUP; IRQ: IRQ4; SCI3: CTS_RTS3; SLCDC: VL1" - IO - - 
      P412 20 SLCDC_SEG16 - - - "Peripheral mode" - - "AGT1: AGTEE1; GPT_OPS: GTOULO; SCI3: CTS3; SLCDC: SEG16" - O - - 
      P413 19 SLCDC_SEG15 - - - "Peripheral mode" - - "GPT_OPS: GTOUUP; SLCDC: SEG15" - O - - 
      P414 18 - - - - Disabled - - "GPT0: GTIOC0B; IRQ: IRQ9; SLCDC: SEG14" - None - - 
      P415 17 - - - - Disabled - - "GPT0: GTIOC0A; IRQ: IRQ8; SLCDC: SEG13; USB FS: USB_VBUSEN" - None - - 
      P500 76 - - - - Disabled - - "ADC0: AN021; AGT0: AGTOA0; CAC: CACREF; CMPOUT: VCOUT; CTSU: TSCAP; GPT_OPS: GTIU; QSPI: QSPCLK; SCI0: CTS0; SLCDC: SEG46; USB FS: USB_VBUSEN" - None - - 
      P501 77 - - - - Disabled - - "AGT0: AGTOB0; CTSU: TS4; GPT_OPS: GTIV; IRQ: IRQ11; QSPI: QSSL; SLCDC: SEG47; USB FS: USB_OVRCURA" - None - - 
      P502 78 - - - - Disabled - - "CTSU: TS5; GPT_OPS: GTIW; IRQ: IRQ12; QSPI: QIO0; SLCDC: SEG48; USB FS: USB_OVRCURB" - None - - 
      P503 79 - - - - Disabled - - "CTSU: TS6; GPT_POEGC: GTETRGC; QSPI: QIO1; SLCDC: SEG49; USB FS: USB_EXICEN" - None - - 
      P504 80 - - - - Disabled - - "CTSU: TS7; GPT_POEGD: GTETRGD; QSPI: QIO2; SLCDC: SEG50; USB FS: USB_ID" - None - - 
      P505 81 - - - - Disabled - - "CMPOUT: VCOUT; IRQ: IRQ14; QSPI: QIO3; SLCDC: SEG51" - None - - 
      P506 84 - - - - Disabled - - "ADC0: AN020; CTSU: TS8; GPT4: GTIOC4A; IRQ: IRQ13; SCI5: TXD5" - None - - 
      P507 85 - - - - Disabled - - "ADC0: AN019; CTSU: TS9; GPT4: GTIOC4B; SCI5: RXD5; UARTA0: CLKA0" - None - - 
      P508 86 - - - - Disabled - - "ADC0: AN018; CTSU: TS10; SCI5: CTS_RTS5; UARTA0: TxDA0" CS None - - 
      P509 87 - - - - Disabled - - "ADC0: AN017; CTSU: TS11; EXLVD: EXLVD; SCI5: SCK5; UARTA0: RxDA0" - None - - 
      P510 88 ADC0_AN025 - - - "Analog mode" - - "ADC0: AN025; SCI9: TXD9" - I - - 
      P511 89 - - - - Disabled - - "ADC0: AN024; SCI9: RXD9; UARTA1: CLKA1" - None - - 
      P512 90 - - - - Disabled - - "ADC0: AN023; SCI9: CTS_RTS9; UARTA1: TxDA1" - None - - 
      P513 91 - - - - Disabled - - "ADC0: AN022; SCI9: SCK9; UARTA1: RxDA1" - None - - 
      P600 67 - - - - Disabled - - "CAC: CACREF; CLKOUT: CLKOUT; GPT2: GTIOC2B; SLCDC: SEG37" - None - - 
      P601 66 GPIO - - - "Output mode (Initial Low)" - - "GPT2: GTIOC2A; SLCDC: SEG36" - IO - - 
      P602 65 - - - - Disabled - - "SLCDC: SEG35" - None - - 
      P608 59 - - - - Disabled - - "GPT4: GTIOC4B; SCI1: RXD1; SLCDC: SEG32; SSIE0: SSITXD0" - None - - 
      P609 60 GPIO - - - "Output mode (Initial Low)" - - "GPT5: GTIOC5A; SCI1: SCK1; SLCDC: SEG33" - IO - - 
      P610 61 GPIO - - - "Output mode (Initial Low)" - - "GPT5: GTIOC5B; SCI1: CTS_RTS1; SLCDC: SEG34" - IO - - 
      P700 8 SLCDC_SEG11 - - - "Peripheral mode" - - "SLCDC: SEG11" - O - - 
      P708 16 GPIO - - None "Input mode" - - "CAC: CACREF; IRQ: IRQ11; SLCDC: SEG12; SSIE: AUDIO_CLK" BLK IO - - 
      P814 28 - - - - Disabled - - "SYSTEM: USB_DP; UARTA1: RxDA1" - None - - 
      P815 27 - - - - Disabled - - "SYSTEM: USB_DM; UARTA1: TxDA1" - None - - 
      RES 38 SYSTEM_RES - - - - - - - - IO "Read only" - 
      VCC 15 SYSTEM_VCC - - - - - - - - IO "Read only" - 
      VCC 46 SYSTEM_VCC - - - - - - - - IO "Read only" - 
      VCC 62 SYSTEM_VCC - - - - - - - - IO "Read only" - 
      VCC 82 SYSTEM_VCC - - - - - - - - IO "Read only" - 
      VCC_USB 29 SYSTEM_VCC_USB - - - - - - - - IO "Read only" - 
      VCL 64 SYSTEM_VCL - - - - - - - - IO "Read only" - 
      VCL0 9 SYSTEM_VCL0 - - - - - - - - IO "Read only" - 
      VSS 12 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS 45 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS 63 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS 83 SYSTEM_VSS - - - - - - - - IO "Read only" - 
      VSS_USB 26 SYSTEM_VSS_USB - - - - - - - - IO "Read only" - 
    
  User Events
    
  User Event Links
    
  Linker Section Mappings
    *(.bss.g_heap): RAM Uninitialized
    *(.bss.g_main_stack): RAM Uninitialized
    
  Module "I/O Port (r_ioport)"
    Parameter Checking: Default (BSP)
    CCD Support: Not Supported
    
  Module "Segment LCD (r_slcdc)"
    Parameter Checking: Default (BSP)
    
  Module "ADC (r_adc)"
    Parameter Checking: Default (BSP)
    
  Module "UART (r_sci_uart)"
    Parameter Checking: Default (BSP)
    FIFO Support: Disable
    DTC Support: Disable
    Flow Control Support: Disable
    RS-485 Support: Disable
    IrDA Support: Disabled
    
  Module "SPI (r_spi)"
    Parameter Checking: Default (BSP)
    Enable Support for using a transfer API: Enabled
    Enable Transmitting from RXI Interrupt: Disabled
    
  HAL
    Instance "g_ioport I/O Port (r_ioport)"
      Name: g_ioport
      1st Port ELC Trigger Source: Disabled
      2nd Port ELC Trigger Source: Disabled
      3rd Port ELC Trigger Source: Disabled
      4th Port ELC Trigger Source: Disabled
      Pin Configuration Name: g_bsp_pin_cfg
      
    Instance "g_slcdc0 Segment LCD (r_slcdc)"
      General: Name: g_slcdc0
      Clock: Source: LOCO
      Clock: Divisor: (LOCO/SOSC) 256
      Output: Bias method: 1/3 bias
      Output: Timeslice: 4-slice
      Output: Waveform: Waveform A
      Output: Drive method: Internal voltage boosting
      Output: Reference Voltage: Select VL1 or VCC
      Output: Default contrast (if available): 0
      
    Instance "g_adc0 ADC (r_adc)"
      General: Name: g_adc0
      General: Unit: 0
      General: Resolution: 12-Bit
      General: Alignment: Right
      General: Clear after read: On
      General: Mode: Single Scan
      General: Double-trigger: Disabled
      Input: Channel Scan Mask (channel availability varies by MCU): Channel 25
      Input: Group B Scan Mask (channel availability varies by MCU): 
      Interrupts: Normal/Group A Trigger: Software
      Interrupts: Group B Trigger: Disabled
      Interrupts: Group Priority (Valid only in Group Scan Mode): Group A cannot interrupt Group B
      Input: Add/Average Count: Disabled
      Input: Reference Voltage control: VREFH0/VREFH
      Input: Addition/Averaging Mask (channel availability varies by MCU and unit): 
      Input: Sample and Hold: Sample and Hold Channels (Available only on selected MCUs): 
      Input: Sample and Hold: Sample Hold States (Applies only to channels 0, 1, 2): 24
      Input: Window Compare: Window Mode: Disabled
      Input: Window Compare: Event Output: OR
      Input: Window Compare: Window A: Enable: Disabled
      Input: Window Compare: Window A: Channels to compare (channel availability varies by MCU and unit): 
      Input: Window Compare: Window A: Channel comparison mode (channel availability varies by MCU and unit): 
      Input: Window Compare: Window A: Lower Reference: 0
      Input: Window Compare: Window A: Upper Reference: 0
      Input: Window Compare: Window B: Enable: Disabled
      Input: Window Compare: Window B: Channel to compare (channel availability varies by MCU and unit): Channel 0
      Input: Window Compare: Window B: Comparison mode: Less Than or Outside Window
      Input: Window Compare: Window B: Lower Reference: 0
      Input: Window Compare: Window B: Upper Reference: 0
      Interrupts: Callback: adc_callback
      Interrupts: Scan End Interrupt Priority: Priority 2
      Interrupts: Scan End Group B Interrupt Priority: Disabled
      Interrupts: Window Compare A Interrupt Priority: Disabled
      Interrupts: Window Compare B Interrupt Priority: Disabled
      Extra: ADC Ring Buffer: Not Supported
      
    Instance "g_uart9 UART (r_sci_uart)"
      General: Name: g_uart9
      General: Channel: 9
      General: Data Bits: 8bits
      General: Parity: None
      General: Stop Bits: 1bit
      Baud: Baud Rate: 115200
      Baud: Baud Rate Modulation: Disabled
      Baud: Max Error (%): 5
      Flow Control: CTS/RTS Selection: Hardware RTS
      Flow Control: Software RTS Port: Disabled
      Flow Control: Software RTS Pin: Disabled
      Extra: Clock Source: Internal Clock
      Extra: Start bit detection: Falling Edge
      Extra: Noise Filter: Disable
      Extra: Receive FIFO Trigger Level: Max
      Extra: IrDA: Enable: Disabled
      Extra: IrDA: RXD Polarity Switching: Normal
      Extra: IrDA: TXD Polarity Switching: Normal
      Extra: RS-485: DE Pin: Disable
      Extra: RS-485: DE Pin Polarity: Active High
      Extra: RS-485: DE Port Number: Disabled
      Extra: RS-485: DE Pin Number: Disabled
      Interrupts: Callback: uart9_callback
      Interrupts: Receive Interrupt Priority: Priority 2
      Interrupts: Transmit Data Empty Interrupt Priority: Priority 2
      Interrupts: Transmit End Interrupt Priority: Priority 2
      Interrupts: Error Interrupt Priority: Priority 2
      
    Instance "g_spi0 SPI (r_spi)"
      Name: g_spi0
      Channel: 0
      Receive Interrupt Priority: Priority 2
      Transmit Buffer Empty Interrupt Priority: Priority 2
      Transfer Complete Interrupt Priority: Priority 2
      Error Interrupt Priority: Priority 2
      Operating Mode: Master
      Clock Phase: Data sampling on odd edge, data variation on even edge
      Clock Polarity: Low when idle
      Mode Fault Error: Disable
      Bit Order: MSB First
      Callback: spi_callback
      SPI Mode: Clock Synchronous Operation
      Full or Transmit Only Mode: Full Duplex
      Slave Select Polarity: Active Low
      Select SSL(Slave Select): SSL0
      MOSI Idle State: MOSI Idle Value Fixing Disable
      Parity Mode: Disabled
      Byte Swapping: Disable
      Bitrate: 25000000
      Clock Delay: 1 Clock
      SSL Negation Delay: 1 Clock
      Next Access Delay: 1 Clock
      
