/*
 * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
 *
 * @file     ./out/R7FA4L1BD.h
 * @brief    CMSIS HeaderFile
 * @version  1.10.03
 */

/** @addtogroup Renesas Electronics Corporation
 * @{
 */

/** @addtogroup R7FA4L1BD
 * @{
 */

#ifndef R7FA4L1BD_H
 #define R7FA4L1BD_H

 #ifdef __cplusplus
extern "C" {
 #endif

/** @addtogroup Configuration_of_CMSIS
 * @{
 */

/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
 #define __CM33_REV                0x0004U /*!< CM33 Core Revision                                                        */
 #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
 #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
 #define __MPU_PRESENT             1       /*!< MPU present                                                               */
 #define __FPU_PRESENT             1       /*!< FPU present                                                               */
 #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
 #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
 #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */

/** @} */ /* End of group Configuration_of_CMSIS */

 #include "core_cm33.h"                    /*!< ARM Cortex-M33 processor and core peripherals                             */
 #include "system.h"                       /*!< R7FA4L1BD System                                                          */

 #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
  #define __IM     __I
 #endif
 #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
  #define __OM     __O
 #endif
 #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
  #define __IOM    __IO
 #endif

/* ========================================  Start of section using anonymous unions  ======================================== */
 #if defined(__CC_ARM)
  #pragma push
  #pragma anon_unions
 #elif defined(__ICCARM__)
  #pragma language=extended
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
 #elif defined(__GNUC__)

/* anonymous unions are enabled by default */
 #elif defined(__TMS470__)

/* anonymous unions are enabled by default */
 #elif defined(__TASKING__)
  #pragma warning 586
 #elif defined(__CSMC__)

/* anonymous unions are enabled by default */
 #else
  #warning Not supported compiler type
 #endif

/* =========================================================================================================================== */
/* ================                              Device Specific Cluster Section                              ================ */
/* =========================================================================================================================== */

/** @addtogroup Device_Peripheral_clusters
 * @{
 */

/**
 * @brief R_BUS_CSa [CSa] (CS Registers)
 */
typedef struct
{
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */

        struct
        {
            __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
            uint16_t             : 2;
            __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
            uint16_t             : 4;
            __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
            __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
            uint16_t             : 5;
            __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
        } MOD_b;
    };

    union
    {
        __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */

        struct
        {
            __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
            uint32_t                : 5;
            __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
            uint32_t                : 5;
            __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
            uint32_t                : 3;
            __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
            uint32_t                : 3;
        } WCR1_b;
    };

    union
    {
        __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */

        struct
        {
            __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
            uint32_t              : 1;
            __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
            uint32_t              : 1;
            __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
            uint32_t              : 1;
            __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
            uint32_t              : 2;
            __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
            uint32_t              : 1;
            __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
            uint32_t              : 1;
            __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
            uint32_t              : 1;
            __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
            uint32_t              : 1;
        } WCR2_b;
    };
    __IM uint32_t RESERVED1;
} R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_CSb [CSb] (CS Registers)
 */
typedef struct
{
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */

        struct
        {
            __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
            uint16_t             : 3;
            __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
            uint16_t             : 2;
            __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
            uint16_t             : 3;
            __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
            uint16_t             : 3;
        } CR_b;
    };
    __IM uint16_t RESERVED1[3];

    union
    {
        __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */

        struct
        {
            __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
            uint16_t            : 4;
            __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
            uint16_t            : 4;
        } REC_b;
    };
    __IM uint16_t RESERVED2[2];
} R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
 */
typedef struct
{
    union
    {
        __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */

        struct
        {
            __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
            uint8_t             : 3;
            __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
            uint8_t             : 2;
        } SDCCR_b;
    };

    union
    {
        __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */

        struct
        {
            __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
            uint8_t             : 7;
        } SDCMOD_b;
    };

    union
    {
        __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */

        struct
        {
            __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
            uint8_t          : 7;
        } SDAMOD_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint32_t RESERVED1[3];

    union
    {
        __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */

        struct
        {
            __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
            uint8_t            : 7;
        } SDSELF_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */

        struct
        {
            __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
            __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
                                        *   Setting. ( REFW+1 Cycles )                                                */
        } SDRFCR_b;
    };

    union
    {
        __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */

        struct
        {
            __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
            uint8_t            : 7;
        } SDRFEN_b;
    };
    __IM uint8_t  RESERVED4;
    __IM uint32_t RESERVED5[2];

    union
    {
        __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */

        struct
        {
            __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
            uint8_t             : 7;
        } SDICR_b;
    };
    __IM uint8_t  RESERVED6;
    __IM uint16_t RESERVED7;

    union
    {
        __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */

        struct
        {
            __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
            __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
            __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
                                        *   )                                                                         */
            uint16_t : 5;
        } SDIR_b;
    };
    __IM uint16_t RESERVED8;
    __IM uint32_t RESERVED9[6];

    union
    {
        __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */

        struct
        {
            __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
            uint8_t           : 6;
        } SDADR_b;
    };
    __IM uint8_t  RESERVED10;
    __IM uint16_t RESERVED11;

    union
    {
        __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */

        struct
        {
            __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
            uint32_t           : 5;
            __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
            __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
            __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
            uint32_t           : 2;
            __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
            uint32_t           : 13;
        } SDTR_b;
    };

    union
    {
        __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */

        struct
        {
            __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
            uint16_t          : 1;
        } SDMOD_b;
    };
    __IM uint16_t RESERVED12;
    __IM uint32_t RESERVED13;

    union
    {
        __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */

        struct
        {
            __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
            uint8_t            : 2;
            __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
            __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
            uint8_t            : 3;
        } SDSR_b;
    };
    __IM uint8_t  RESERVED14;
    __IM uint16_t RESERVED15;
} R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */

/**
 * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
 */
typedef struct
{
    union
    {
        __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */

        struct
        {
            __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
        } ADD_b;
    };

    union
    {
        union
        {
            __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */

            struct
            {
                __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
                uint8_t              : 6;
                __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
            } STAT_b;
        };

        union
        {
            __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */

            struct
            {
                __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
                uint8_t             : 7;
            } RW_b;
        };
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2[2];
} R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
 */
typedef struct
{
    union
    {
        __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */

        struct
        {
            __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
        } ADD_b;
    };

    union
    {
        __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */

        struct
        {
            __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
            uint8_t              : 7;
        } RW_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2[2];
} R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
 */
typedef struct
{
    union
    {
        __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */

        struct
        {
            __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
            __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
            uint8_t                : 1;
            __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
            __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
            __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
            uint8_t                : 2;
        } STAT_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2;

    union
    {
        union
        {
            __IOM uint32_t IRQEN;      /*!< (@ 0x00000008) BUS Error IRQ Enable                                       */

            struct
            {
                __IOM uint32_t EN : 1; /*!< [0..0] Bus interrupt request permission setting to ICU when
                                        *   a bus error occurs                                                        */
                uint32_t : 31;
            } IRQEN_b;
        };

        union
        {
            __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */

            struct
            {
                __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
                __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
                uint8_t                : 1;
                __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
                __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
                __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
                uint8_t                : 2;
            } CLR_b;
        };
    };
    __IM uint32_t RESERVED3;
} R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
 */
typedef struct
{
    __IM uint8_t RESERVED[36];

    union
    {
        __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */

        struct
        {
            __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
            uint8_t                : 7;
        } STAT_b;
    };
    __IM uint8_t RESERVED1[7];

    union
    {
        __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */

        struct
        {
            __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
            uint8_t                : 7;
        } CLR_b;
    };
} R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */

/**
 * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
 */
typedef struct
{
    __IM uint32_t RESERVED[2];

    union
    {
        __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } MRE0BI_b;
    };
    __IM uint32_t RESERVED1;

    union
    {
        __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } FLBI_b;
    };
    __IM uint32_t RESERVED2[3];

    union
    {
        __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } S0BI_b;
    };
    __IM uint32_t RESERVED3;

    union
    {
        __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } S1BI_b;
    };
    __IM uint32_t RESERVED4;

    union
    {
        __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } S2BI_b;
    };
    __IM uint32_t RESERVED5;

    union
    {
        __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } S3BI_b;
    };
    __IM uint32_t RESERVED6[3];

    union
    {
        __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } STBYSBI_b;
    };
    __IM uint32_t RESERVED7;

    union
    {
        union
        {
            __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } ECBI_b;
        };

        union
        {
            __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } SPI0BI_b;
        };
    };
    __IM uint32_t RESERVED8;

    union
    {
        union
        {
            __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } EOBI_b;
        };

        union
        {
            __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } SPI1BI_b;
        };
    };
    __IM uint32_t RESERVED9;

    union
    {
        __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } PBBI_b;
    };
    __IM uint32_t RESERVED10;

    union
    {
        union
        {
            __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } PABI_b;
        };

        union
        {
            __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
                uint32_t            : 31;
            } CPU0SAHBI_b;
        };
    };
    __IM uint32_t RESERVED11;

    union
    {
        __IOM uint32_t PIBI;           /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } PIBI_b;
    };
    __IM uint32_t RESERVED12;

    union
    {
        __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
            uint32_t            : 31;
        } PSBI_b;
    };
} R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */

/**
 * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
 */
typedef struct
{
    union
    {
        union
        {
            __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
                uint32_t            : 30;
            } FHBI_b;
        };

        union
        {
            __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */

            struct
            {
                __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
                uint32_t            : 30;
            } MRC0BI_b;
        };
    };
    __IM uint32_t RESERVED[5];

    union
    {
        __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
            uint32_t            : 30;
        } S0BI_b;
    };
    __IM uint32_t RESERVED1;

    union
    {
        __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */

        struct
        {
            __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
            uint32_t            : 30;
        } S1BI_b;
    };
} R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */

/**
 * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
 */
typedef struct
{
    union
    {
        __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */

        struct
        {
            __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
        } ADD_b;
    };

    union
    {
        __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
                                         *                  Write.                                                     */

        struct
        {
            __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
                                         *   Status.                                                                   */
            uint8_t : 7;
        } RW_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2[2];
} R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
 */
typedef struct
{
    union
    {
        __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */

        struct
        {
            __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
            __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
            __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
            uint16_t                : 13;
        } BUSOAD_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
        } BUSOADPT_b;
    };
    __IM uint16_t RESERVED1[5];

    union
    {
        __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
                                        *                  Register.                                                  */

        struct
        {
            __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
            uint16_t           : 7;
            __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
        } MSAOAD_b;
    };
    __IM uint16_t RESERVED2;

    union
    {
        __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
        } MSAPT_b;
    };
} R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */

/**
 * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
 */
typedef struct
{
    union
    {
        __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */

        struct
        {
            __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
            __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
            __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
            __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
            __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
            __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
            __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
            __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
            __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
            __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
            __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
            __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
            __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
            __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
            __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
            __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
            __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
            __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
            __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
            __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
            __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
            __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
            __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
            __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
            __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
            __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
            __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
            __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
            __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
            __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
            __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
            __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
        } STAT_b;
    };
    __IM uint32_t RESERVED;

    union
    {
        __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */

        struct
        {
            __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
            __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
            __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
            __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
            __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
            __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
            __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
            __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
            __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
            __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
            __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
            __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
            __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
            __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
            __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
            __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
            __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
            __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
            __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
            __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
            __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
            __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
            __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
            __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
            __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
            __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
            __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
            __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
            __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
            __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
            __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
            __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
        } CLR_b;
    };
} R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */

/**
 * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
 */
typedef struct
{
    union
    {
        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */

        struct
        {
            uint16_t             : 15;
            __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
        } CNT_b;
    };
    __IM uint16_t RESERVED;
} R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */

/**
 * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
 */
typedef struct
{
    union
    {
        __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */

        struct
        {
            __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
            uint16_t              : 2;
            __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
            uint16_t              : 10;
        } CNT_b;
    };
    __IM uint16_t RESERVED;
} R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */

/**
 * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
 */
typedef struct
{
    union
    {
        __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */

        struct
        {
            __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
            __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
            __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
            __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
        } NCFG_b;
    };

    union
    {
        __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */

        struct
        {
            __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
            __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
            __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
            uint32_t               : 4;
            __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
            __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
            __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
            __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
            __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
            __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
            __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
            __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
            __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
            __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
            __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
            __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
                                         *   enable                                                                    */
            uint32_t            : 1;
            __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
            __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
            __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
            __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
            uint32_t            : 3;
            __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
            __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
        } CTR_b;
    };

    union
    {
        __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */

        struct
        {
            __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
            __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
            __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
            __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
            __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
            __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
            __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
            __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
            __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
            uint32_t               : 7;
            __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
            __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
        } STS_b;
    };

    union
    {
        __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */

        struct
        {
            __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
            __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
            __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
            __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
            __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
            __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
            __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
            __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
            __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
            __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
            __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
            __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
            __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
            __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
            __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
            uint32_t             : 1;
            __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
            uint32_t             : 1;
        } ERFL_b;
    };
} R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
 */
typedef struct
{
    union
    {
        __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */

        struct
        {
            __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
            __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
            uint32_t              : 3;
            __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
            uint32_t              : 4;
            __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
            uint32_t              : 4;
        } DCFG_b;
    };

    union
    {
        __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */

        struct
        {
            __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
            uint32_t              : 5;
            __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
            __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
            __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
            uint32_t              : 5;
            __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
            uint32_t              : 4;
            __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
            __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
            __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
            uint32_t              : 1;
        } FDCFG_b;
    };

    union
    {
        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */

        struct
        {
            __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
            __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
            uint32_t              : 30;
        } FDCTR_b;
    };

    union
    {
        __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */

        struct
        {
            __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
            __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
            __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
            uint32_t             : 5;
            __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
            __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
            __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
        } FDSTS_b;
    };

    union
    {
        __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */

        struct
        {
            __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
            uint32_t             : 3;
            __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
            uint32_t             : 4;
        } FDCRC_b;
    };
    __IM uint32_t RESERVED[3];
} R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */

/**
 * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
 */
typedef struct
{
    union
    {
        __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */

        struct
        {
            __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
            __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
            __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
            __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
        } ID_b;
    };

    union
    {
        __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */

        struct
        {
            __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
            __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
            __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
            __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
        } M_b;
    };

    union
    {
        __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */

        struct
        {
            __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
            uint32_t                : 3;
            __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
            __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
                                          *   Pointer                                                                   */
            uint32_t               : 2;
            __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
            __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
        } P0_b;
    };

    union
    {
        __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */

        struct
        {
            __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
            uint32_t               : 23;
        } P1_b;
    };
} R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
 */
typedef struct
{
    union
    {
        __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */

        struct
        {
            __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
            __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
            uint32_t           : 6;
            __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
        } ACC0_b;
    };

    union
    {
        __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */

        struct
        {
            __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
            __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
            uint32_t           : 14;
        } ACC1_b;
    };
} R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */

/**
 * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
 */
typedef struct
{
    union
    {
        __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */

        struct
        {
            __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
            uint32_t            : 1;
            __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
            __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
        } ID_b;
    };

    union
    {
        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */

        struct
        {
            __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
            uint32_t            : 12;
            __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
        } PTR_b;
    };

    union
    {
        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */

        struct
        {
            __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
            __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
            __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
            uint32_t            : 5;
            __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
            uint32_t            : 6;
            __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
        } FDSTS_b;
    };

    union
    {
        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */

        struct
        {
            __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
        } DF_b[64];
    };
} R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */

/**
 * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
 */
typedef struct
{
    union
    {
        __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */

        struct
        {
            __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
            __IOM uint32_t THLEN : 1;  /*!< [29..29] THL Entry enable                                                 */
            __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
            __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
        } ID_b;
    };

    union
    {
        __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */

        struct
        {
            __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
            uint32_t             : 12;
            __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
        } PTR_b;
    };

    union
    {
        __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */

        struct
        {
            __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
            __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
            __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
            uint32_t             : 5;
            __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
            uint32_t             : 6;
            __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
        } FDSTS_b;
    };

    union
    {
        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */

        struct
        {
            __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
        } DF_b[64];
    };
} R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */

/**
 * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
 */
typedef struct
{
    union
    {
        __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */

        struct
        {
            __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
            __IOM uint32_t THLEN : 1;  /*!< [29..29] Tx History List Entry                                            */
            __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
            __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
        } ID_b;
    };

    union
    {
        __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */

        struct
        {
            __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
            uint32_t             : 12;
            __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
        } PTR_b;
    };

    union
    {
        __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */

        struct
        {
            __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
            __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
            __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
            uint32_t             : 5;
            __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
            uint32_t             : 6;
            __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
        } FDCTR_b;
    };

    union
    {
        __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */

        struct
        {
            __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
        } DF_b[64];
    };
} R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */

/**
 * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
 */
typedef struct
{
    union
    {
        __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */

        struct
        {
            __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
            uint32_t            : 1;
            __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
            __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
        } ID_b;
    };

    union
    {
        __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */

        struct
        {
            __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
            uint32_t            : 12;
            __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
        } PTR_b;
    };

    union
    {
        __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */

        struct
        {
            __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
            __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
            __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
            uint32_t            : 5;
            __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
            uint32_t            : 6;
            __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
        } FDSTS_b;
    };

    union
    {
        __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */

        struct
        {
            __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
        } DF_b[64];
    };
} R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */

/**
 * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
 */
typedef struct
{
    __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
    __IM uint32_t               RESERVED[104];
} R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */

/**
 * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
 */
typedef struct
{
    union
    {
        __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */

        struct
        {
            __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
            uint8_t          : 5;
            __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
            __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
        } BY_b;
    };
    __IM uint8_t RESERVED;
} R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */

/**
 * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
 */
typedef struct
{
    union
    {
        __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */

        struct
        {
            __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
            uint16_t           : 7;
        } HA_b;
    };
    __IM uint16_t RESERVED;
} R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */

/**
 * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
 */
typedef struct
{
    union
    {
        __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */

        struct
        {
            __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
                                        *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
        } L_b;
    };

    union
    {
        __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */

        struct
        {
            __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
            __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
            __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
            uint8_t            : 5;
        } U_b;
    };
} R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */

/**
 * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
 */
typedef struct
{
    union
    {
        __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */

        struct
        {
            __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
            __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
            __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
            __IOM uint16_t PP     : 1; /*!< [3..3] Privilege protection                                               */
            uint16_t              : 12;
        } AC_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */

        struct
        {
            __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
                                        *   NOTE: Some low-order bits are fixed to 0.                                 */
        } S_b;
    };

    union
    {
        __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */

        struct
        {
            __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
                                        *   end, for use in region determination. NOTE: Some low-order
                                        *   bits are fixed to 1.                                                      */
        } E_b;
    };
    __IM uint32_t RESERVED1;
} R_MPU_MMPU_GROUP_REGION_Type;        /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..CEU] MMPU Registers)
 */
typedef struct
{
    union
    {
        __IOM uint16_t EN;             /*!< (@ 0x00000000) MMPU enable register                                       */

        struct
        {
            __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable                                      */
            uint16_t              : 7;
            __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                        *   stored.                                                                   */
        } EN_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t ENPT;            /*!< (@ 0x00000004) MMPU enable protect register                               */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN                                          */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                         *   stored.                                                                   */
        } ENPT_b;
    };
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint16_t RPT;             /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure                   */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                         *   stored.                                                                   */
        } RPT_b;
    };
    __IM uint16_t RESERVED2;

    union
    {
        __IOM uint16_t RPT_SEC;         /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only)           */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                         *   stored.                                                                   */
        } RPT_SEC_b;
    };
    __IM uint16_t RESERVED3;
    __IM uint32_t RESERVED4[60];
    __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control                                     */
    __IM uint32_t RESERVED5[32];
} R_MPU_MMPU_GROUP_Type;                          /*!< Size = 512 (0x200)                                                        */

/**
 * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
 */
typedef struct
{
    union
    {
        __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
                                        *                  Register                                                   */

        struct
        {
            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
            uint16_t           : 7;
            __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
                                        *   stored.                                                                   */
        } OAD_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */

        struct
        {
            __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
            uint16_t              : 7;
            __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
            uint16_t              : 7;
        } CTL_b;
    };

    union
    {
        __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                         *   stored.                                                                   */
        } PT_b;
    };

    union
    {
        __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */

        struct
        {
            __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
                                           *   The low-order 2 bits are fixed to 0.                                      */
        } SA_b;
    };

    union
    {
        __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */

        struct
        {
            __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
                                           *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
                                           *   The low-order 2 bits are fixed to 1.                                      */
        } EA_b;
    };
} R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
 */
typedef struct
{
    union
    {
        union
        {
            __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */

            struct
            {
                __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
                __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
                __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
                uint32_t             : 1;
                __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
                __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
                __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
                uint32_t             : 3;
                __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
                __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
                __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
                __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
                __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
                uint32_t             : 7;
                __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
                                           *   function. For individual pin functions, see the MPC table                 */
                uint32_t : 3;
            } PmnPFS_b;
        };

        struct
        {
            union
            {
                struct
                {
                    __IM uint16_t RESERVED;

                    union
                    {
                        __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */

                        struct
                        {
                            __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
                            __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
                            __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
                            uint16_t             : 1;
                            __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
                            __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
                            __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
                            uint16_t             : 3;
                            __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
                            __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
                            __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
                            __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
                        } PmnPFS_HA_b;
                    };
                };

                struct
                {
                    __IM uint16_t RESERVED1;
                    __IM uint8_t  RESERVED2;

                    union
                    {
                        __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */

                        struct
                        {
                            __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
                            __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
                            __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
                            uint8_t             : 1;
                            __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
                            __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
                            __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
                            uint8_t             : 1;
                        } PmnPFS_BY_b;
                    };
                };
            };
        };
    };
} R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */

/**
 * @brief R_PFS_PORT [PORT] (Port [0..14])
 */
typedef struct
{
    __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
} R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */

/**
 * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
 */
typedef struct
{
    __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
} R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */

/**
 * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
 */
typedef struct
{
    union
    {
        __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */

        struct
        {
            __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
            __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
            uint8_t            : 1;
            __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
            uint8_t            : 1;
            __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
        } RTCCR_b;
    };
    __IM uint8_t RESERVED;
} R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */

/**
 * @brief R_RTC_CP [CP] (Capture registers)
 */
typedef struct
{
    __IM uint8_t RESERVED[2];

    union
    {
        union
        {
            __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */

            struct
            {
                __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
                                         *   seconds                                                                   */
                __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
                                         *   seconds                                                                   */
                uint8_t : 1;
            } RSEC_b;
        };

        union
        {
            __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */

            struct
            {
                __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
                                           *   value when a time capture event is detected.                              */
            } BCNT0_b;
        };
    };
    __IM uint8_t RESERVED1;

    union
    {
        union
        {
            __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */

            struct
            {
                __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
                                         *   minutes                                                                   */
                __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
                                         *   minutes                                                                   */
                uint8_t : 1;
            } RMIN_b;
        };

        union
        {
            __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */

            struct
            {
                __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
                                           *   value when a time capture event is detected.                              */
            } BCNT1_b;
        };
    };
    __IM uint8_t RESERVED2;

    union
    {
        union
        {
            __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */

            struct
            {
                __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
                                        *   minutes                                                                   */
                __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
                                        *   minutes                                                                   */
                __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
                uint8_t         : 1;
            } RHR_b;
        };

        union
        {
            __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */

            struct
            {
                __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
                                           *   value when a time capture event is detected.                              */
            } BCNT2_b;
        };
    };
    __IM uint8_t RESERVED3[3];

    union
    {
        union
        {
            __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */

            struct
            {
                __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
                __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
                uint8_t             : 2;
            } RDAY_b;
        };

        union
        {
            __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */

            struct
            {
                __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
                                           *   value when a time capture event is detected.                              */
            } BCNT3_b;
        };
    };
    __IM uint8_t RESERVED4;

    union
    {
        __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */

        struct
        {
            __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
            __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
                                        *   months                                                                    */
            uint8_t : 3;
        } RMON_b;
    };
    __IM uint8_t RESERVED5[3];
} R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
 */
typedef struct
{
    union
    {
        __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */

        struct
        {
            uint16_t             : 8;
            __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
            __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
            uint16_t             : 6;
        } E_b;
    };

    union
    {
        __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */

        struct
        {
            __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
        } N_b;
    };
} R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */

/**
 * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
 */
typedef struct
{
    union
    {
        __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */

        struct
        {
            __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
            __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
            __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
            uint8_t              : 1;
            __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
            __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
            __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
            __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
        } AGTCR_b;
    };

    union
    {
        __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */

        struct
        {
            __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
            __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
            __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
            uint8_t              : 1;
        } AGTMR1_b;
    };

    union
    {
        __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */

        struct
        {
            __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
                                        *   ratio                                                                     */
            uint8_t           : 4;
            __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
        } AGTMR2_b;
    };

    union
    {
        __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */

        struct
        {
            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
            uint8_t            : 2;
            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
            uint8_t            : 3;
        } AGTIOSEL_ALT_b;
    };

    union
    {
        __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */

        struct
        {
            __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
                                        *   mode.                                                                     */
            uint8_t             : 1;
            __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
            uint8_t             : 1;
            __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
            __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
        } AGTIOC_b;
    };

    union
    {
        __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */

        struct
        {
            uint8_t            : 2;
            __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
            uint8_t            : 5;
        } AGTISR_b;
    };

    union
    {
        __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */

        struct
        {
            __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
            __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
            __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
            uint8_t              : 1;
            __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
            __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
            __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
            uint8_t              : 1;
        } AGTCMSR_b;
    };

    union
    {
        __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */

        struct
        {
            __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
            uint8_t            : 2;
            __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
            uint8_t            : 3;
        } AGTIOSEL_b;
    };
} R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */

/**
 * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
 */
typedef struct
{
    union
    {
        __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */

        struct
        {
            __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
                                        *   counter is forcibly stopped and set to FFFFH.                             */
        } AGT_b;
    };

    union
    {
        __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */

        struct
        {
            __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
                                         *   written to the TSTOP bit in the AGTCRn register, set to
                                         *   FFFFH                                                                     */
        } AGTCMA_b;
    };

    union
    {
        __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */

        struct
        {
            __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
                                         *   written to the TSTOP bit in the AGTCR register, set to
                                         *   FFFFH                                                                     */
        } AGTCMB_b;
    };
    __IM uint16_t                 RESERVED;
    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
} R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */

/**
 * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
 */
typedef struct
{
    union
    {
        __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */

        struct
        {
            __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
                                        *   written to the TSTOP bit in the AGTCRn register, the 16-bit
                                        *   counter is forcibly stopped and set to FFFFH.                             */
        } AGT_b;
    };

    union
    {
        __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */

        struct
        {
            __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
                                         *   written to the TSTOP bit in the AGTCRn register, set to
                                         *   FFFFH                                                                     */
        } AGTCMA_b;
    };

    union
    {
        __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */

        struct
        {
            __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
                                         *   written to the TSTOP bit in the AGTCR register, set to
                                         *   FFFFH                                                                     */
        } AGTCMB_b;
    };
    __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
} R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */

/** @} */ /* End of group Device_Peripheral_clusters */

/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */

/** @addtogroup Device_Peripheral_peripherals
 * @{
 */

/* =========================================================================================================================== */
/* ================                                         R_ACMPLP                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Low-Power Analog Comparator (R_ACMPLP)
 */

typedef struct                         /*!< (@ 0x400F4000) R_ACMPLP Structure                                         */
{
    union
    {
        __IOM uint8_t COMPMDR;         /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */

        struct
        {
            __IOM uint8_t C0ENB : 1;   /*!< [0..0] ACMPLP0 Operation Enable                                           */
            __IOM uint8_t C0WDE : 1;   /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
            __IOM uint8_t C0VRF : 1;   /*!< [2..2] ACMPLP0 Reference Voltage Selection                                */
            __IM uint8_t  C0MON : 1;   /*!< [3..3] ACMPLP0 Monitor Flag                                               */
            __IOM uint8_t C1ENB : 1;   /*!< [4..4] ACMPLP1 Operation Enable                                           */
            __IOM uint8_t C1WDE : 1;   /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
            __IOM uint8_t C1VRF : 1;   /*!< [6..6] ACMPLP1 Reference Voltage Selection                                */
            __IM uint8_t  C1MON : 1;   /*!< [7..7] ACMPLP1 Monitor Flag                                               */
        } COMPMDR_b;
    };

    union
    {
        __IOM uint8_t COMPFIR;         /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */

        struct
        {
            __IOM uint8_t C0FCK : 2;   /*!< [1..0] ACMPLP0 Filter Select                                              */
            __IOM uint8_t C0EPO : 1;   /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
            __IOM uint8_t C0EDG : 1;   /*!< [3..3] ACMPLP0 Edge Detection Selection                                   */
            __IOM uint8_t C1FCK : 2;   /*!< [5..4] ACMPLP1 Filter Select                                              */
            __IOM uint8_t C1EPO : 1;   /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
            __IOM uint8_t C1EDG : 1;   /*!< [7..7] ACMPLP1 Edge Detection Selection                                   */
        } COMPFIR_b;
    };

    union
    {
        __IOM uint8_t COMPOCR;         /*!< (@ 0x00000002) ACMPLP Output Control Register                             */

        struct
        {
            uint8_t             : 1;
            __IOM uint8_t C0OE  : 1;   /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
            __IOM uint8_t C0OP  : 1;   /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
            uint8_t             : 2;
            __IOM uint8_t C1OE  : 1;   /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
            __IOM uint8_t C1OP  : 1;   /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
            __IOM uint8_t SPDMD : 1;   /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
        } COMPOCR_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint8_t COMPSEL0;        /*!< (@ 0x00000004) Comparator Input Select Register                           */

        struct
        {
            __IOM uint8_t IVCMP0 : 3;  /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection                                   */
            uint8_t              : 1;
            __IOM uint8_t IVCMP1 : 3;  /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection                                   */
            uint8_t              : 1;
        } COMPSEL0_b;
    };

    union
    {
        __IOM uint8_t COMPSEL1;        /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */

        struct
        {
            __IOM uint8_t IVREF0 : 3;  /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
            uint8_t              : 1;
            __IOM uint8_t IVREF1 : 3;  /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
            __IOM uint8_t C1VRF2 : 1;  /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
        } COMPSEL1_b;
    };
} R_ACMPLP_Type;                       /*!< Size = 6 (0x6)                                                            */

/* =========================================================================================================================== */
/* ================                                          R_ADC0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief A/D Converter (R_ADC0)
 */

typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure                                           */
{
    union
    {
        __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */

        struct
        {
            __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
                                        *   input channel for double triggered operation. The setting
                                        *   is only effective while double trigger mode is selected.                  */
            uint16_t              : 1;
            __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
            __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
            __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
            __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
            __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
            uint16_t              : 1;
            __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
            __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
            __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
        } ADCSR_b;
    };

    union
    {
        __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */

        struct
        {
            __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
                                        *   '1' while scanning.                                                       */
            uint8_t              : 6;
            __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
        } ADREF_b;
    };

    union
    {
        __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */

        struct
        {
            __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
            uint8_t             : 7;
        } ADEXREF_b;
    };

    union
    {
        __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */

        struct
        {
            __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
            __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
            __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
            __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
            __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
            __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
            __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
            __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
            __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
            __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
            __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
            __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
            __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
            __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
            __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
            __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
        } ADANSA_b[2];
    };

    union
    {
        __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
                                        *                  Select Register                                            */

        struct
        {
            __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
            __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
            __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
            __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
            __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
            __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
            __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
        } ADADS_b[2];
    };

    union
    {
        __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
                                        *                  Register                                                   */

        struct
        {
            __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
                                        *   at the only setting of ADC[2:0] bits = 001b or 011b. When
                                        *   average mode is selected by setting the ADADC.AVEE bit
                                        *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
                                        *   = 010b)                                                                   */
            uint8_t            : 4;
            __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
                                        *   by setting the ADADC.AVEE bit to 0, set the addition count
                                        *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
                                        *   can only be used with 12-bit accuracy selected. NOTE: AVEE
                                        *   bit is valid at the only setting of ADC[2:0] bits = 001b
                                        *   or 011b. When average mode is selected by setting the ADADC.AVEE
                                        *   bit to 1, do not set the addition count to three times
                                        *   (ADADC.ADC[2:0] = 010b)                                                   */
        } ADADC_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */

        struct
        {
            uint16_t               : 1;
            __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
            uint16_t               : 1;
            __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
            __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
            uint16_t               : 2;
            __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
            __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
            __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
            uint16_t               : 2;
            __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
            __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
        } ADCER_b;
    };

    union
    {
        __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */

        struct
        {
            __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
                                        *   the A/D conversion start trigger for group B in group scan
                                        *   mode.                                                                     */
            uint16_t            : 2;
            __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
                                        *   start trigger in single scan mode and continuous mode.
                                        *   In group scan mode, the A/D conversion start trigger for
                                        *   group A is selected.                                                      */
            uint16_t : 2;
        } ADSTRGR_b;
    };

    union
    {
        __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */

        struct
        {
            __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
                                        *   Mode Select                                                               */
            __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
                                        *   Mode Select                                                               */
            uint16_t            : 6;
            __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
            __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
            __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
                                        *   Group B in group scan mode.                                               */
            __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
                                        *   Group B in group scan mode.                                               */
            uint16_t             : 2;
            __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
            __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
        } ADEXICR_b;
    };

    union
    {
        __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */

        struct
        {
            __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
            __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
            __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
            __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
            __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
            __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
            __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
            __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
            __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
            __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
            __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
            __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
            __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
            __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
            __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
            __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
        } ADANSB_b[2];
    };

    union
    {
        __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */

        struct
        {
            __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
                                         *   result of A/D conversion in response to the second trigger
                                         *   in double trigger mode.                                                   */
        } ADDBLDR_b;
    };

    union
    {
        __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */

        struct
        {
            __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
                                        *   A/D conversion result of temperature sensor output.                       */
        } ADTSDR_b;
    };

    union
    {
        __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */

        struct
        {
            __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
                                        *   A/D result of internal reference voltage.                                 */
        } ADOCDR_b;
    };

    union
    {
        union
        {
            __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */

            struct
            {
                __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified). The format for
                                           *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
                __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
            } ADRD_RIGHT_b;
        };

        union
        {
            __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */

            struct
            {
                __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
                __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (left-justified). The format for
                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
            } ADRD_LEFT_b;
        };
    };

    union
    {
        __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */

        struct
        {
            __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
                                        *   storing the result of A/D conversion.                                     */
        } ADDR_b[29];
    };
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2;
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */

        struct
        {
            __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
        } ADAMPOFF_b;
    };

    union
    {
        __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */

        struct
        {
            __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
            __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
            uint8_t            : 6;
        } ADTSTPR_b;
    };

    union
    {
        __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */

        struct
        {
            __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
            uint16_t              : 3;
            __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
            uint16_t              : 2;
            __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
        } ADDDACER_b;
    };

    union
    {
        __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */

        struct
        {
            __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
                                        *   Setting Set the sampling time (4 to 255 states)                           */
            __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
            __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
            __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
            uint16_t              : 5;
        } ADSHCR_b;
    };

    union
    {
        __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */

        struct
        {
            __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
                                        *   only for channel.                                                         */
            uint16_t             : 1;
            __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
            uint16_t             : 2;
            __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
                                        *   for adjustment to hardening of process.                                   */
            uint16_t              : 1;
            __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
                                        *   power save bit for A/D hard macro to hardening of process.                */
            __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
                                        *   bit for A/D hard macro to hardening of process.                           */
            __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
                                        *   bit for A/D hard macro to hardening of process.                           */
        } ADEXTSTR_b;
    };

    union
    {
        __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */

        struct
        {
            __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
            __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
                                           *   amplifier test.Refreshing the pressure switch that opens
                                           *   for the DAC output voltage charge period when the amplifier
                                           *   of the S&H circuit is tested only for the channel is set.                 */
            uint16_t            : 1;
            __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
                                           *   bit.                                                                      */
            __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
                                           *   bit                                                                       */
            uint16_t                 : 1;
            __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
                                           *   module Details are described to the bit explanation.                      */
            __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
                                           *   bit explanation.                                                          */
        } ADTSTRA_b;
    };

    union
    {
        __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */

        struct
        {
            __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
                                        *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
            uint16_t : 1;
        } ADTSTRB_b;
    };

    union
    {
        __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */

        struct
        {
            __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
                                         *   analog module.                                                            */
            uint16_t               : 4;
            __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
            uint16_t               : 3;
        } ADTSTRC_b;
    };

    union
    {
        __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */

        struct
        {
            __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
                                         *   corresponds to ADVAL 16 input of A/D analog module.                       */
            uint16_t : 15;
        } ADTSTRD_b;
    };

    union
    {
        __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */

        struct
        {
            __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
            uint16_t              : 10;
        } ADSWTSTR0_b;
    };

    union
    {
        __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */

        struct
        {
            __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
            __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
            uint16_t              : 10;
        } ADSWTSTR1_b;
    };

    union
    {
        __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */

        struct
        {
            __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
                                          *   (ANEX0 switch)                                                            */
            __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
                                          *   (ANEX1 switch).                                                           */
            uint16_t                : 2;
            __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
            __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
            __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
            uint16_t                : 1;
            __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
            __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
            __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
            __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
            __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
            uint16_t                : 3;
        } ADSWTSTR2_b;
    };
    __IM uint16_t RESERVED4;

    union
    {
        __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */

        struct
        {
            __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
            __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
            uint8_t              : 3;
        } ADDISCR_b;
    };

    union
    {
        __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */

        struct
        {
            __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
                                        *   the pressure switch in A/D analog module is set.                          */
            uint8_t               : 1;
            __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
            uint8_t               : 1;
        } ADSWCR_b;
    };

    union
    {
        __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */

        struct
        {
            __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
                                        *   Select                                                                    */
            uint8_t : 7;
        } ADSHMSR_b;
    };

    union
    {
        __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */

        struct
        {
            __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
            uint8_t            : 6;
        } ADICR_b;
    };

    union
    {
        __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */

        struct
        {
            uint8_t             : 1;
            __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
            uint8_t             : 6;
        } ADACSR_b;
    };
    __IM uint8_t RESERVED5;

    union
    {
        __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */

        struct
        {
            __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
                                         *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
                                         *   set to 01b (group scan mode). If the bits are set to any
                                         *   other values, proper operation is not guaranteed.                         */
            __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
                                         *   when PGS = 0.)                                                            */
            uint16_t               : 6;
            __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
            uint16_t               : 6;
            __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
                                         *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
                                         *   has been set to 1, single scan is performed continuously
                                         *   for group B regardless of the setting of the GBRSCN bit.                  */
        } ADGSPCR_b;
    };

    union
    {
        __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
                                        *                  Scan)                                                      */

        struct
        {
            __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
            __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
        } ADGSCS_b;
    };

    union
    {
        __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */

        struct
        {
            __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
                                          *   the result of A/D conversion in response to the respective
                                          *   triggers during extended operation in double trigger mode.                */
        } ADDBLDRA_b;
    };

    union
    {
        __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */

        struct
        {
            __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
                                          *   the result of A/D conversion in response to the respective
                                          *   triggers during extended operation in double trigger mode.                */
        } ADDBLDRB_b;
    };

    union
    {
        __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */

        struct
        {
            uint8_t             : 7;
            __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
        } ADSER_b;
    };
    __IM uint8_t RESERVED6;

    union
    {
        __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
                                        *                  Control Register                                           */

        struct
        {
            __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
            uint8_t             : 2;
            __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
            uint8_t             : 2;
            __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
        } ADHVREFCNT_b;
    };
    __IM uint8_t RESERVED7;

    union
    {
        __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
                                        *                  Register                                                   */

        struct
        {
            __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
                                        *   result.This bit is valid when both window A operation and
                                        *   window B operation are enabled.                                           */
            uint8_t              : 3;
            __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
            __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
            uint8_t              : 2;
        } ADWINMON_b;
    };
    __IM uint8_t  RESERVED8;
    __IM uint16_t RESERVED9;

    union
    {
        __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */

        struct
        {
            __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
                                        *   are valid when both window A and window B are enabled (CMPAE
                                        *   = 1 and CMPBE = 1).                                                       */
            uint16_t              : 7;
            __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
            uint16_t              : 1;
            __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
            uint16_t              : 1;
            __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
            __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
            __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
        } ADCMPCR_b;
    };

    union
    {
        __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
                                        *                  Select Register                                            */

        struct
        {
            __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
            __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
            uint8_t              : 6;
        } ADCMPANSER_b;
    };

    union
    {
        __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
                                        *                  Comparison Condition Setting Register                      */

        struct
        {
            __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
                                        *   Condition Select                                                          */
            __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
                                        *   Select                                                                    */
            uint8_t : 6;
        } ADCMPLER_b;
    };

    union
    {
        __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
                                          *                  Register                                                   */

        struct
        {
            __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
            __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
            __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
            __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
            __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
            __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
            __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
            __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
            __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
            __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
            __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
            __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
            __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
            __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
            __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
            __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
        } ADCMPANSR_b[2];
    };

    union
    {
        __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
                                           *                  Setting Register                                           */

        struct
        {
            __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
            __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
            __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
            __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
            __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
            __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
            __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
        } ADCMPLR_b[2];
    };

    union
    {
        __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
                                           *                  Setting Register                                           */

        struct
        {
            __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
                                           *   compare window A function is used. ADCMPDR0 sets the lower-side
                                           *   level of window A.                                                        */
        } ADCMPDR0_b;
    };

    union
    {
        __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
                                           *                  Setting Register                                           */

        struct
        {
            __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
                                           *   compare window A function is used. ADCMPDR1 sets the upper-side
                                           *   level of window A..                                                       */
        } ADCMPDR1_b;
    };

    union
    {
        __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
                                            *                  Register                                                   */

        struct
        {
            __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
            __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
            __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
            __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
            __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
            __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
            __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
        } ADCMPSR_b[2];
    };

    union
    {
        __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
                                         *                  Channel Status Register                                    */

        struct
        {
            __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
                                         *   this bit indicates the temperature sensor output comparison
                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
                                         *   time.                                                                     */
            __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
                                         *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
                                         *   this bit indicates the temperature sensor output comparison
                                         *   result. When window A operation is disabled (ADCMPCR.CMPAE
                                         *   = 0b), comparison conditions for CMPSTTSA are not met any
                                         *   time.                                                                     */
            uint8_t : 6;
        } ADCMPSER_b;
    };
    __IM uint8_t RESERVED10;

    union
    {
        __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
                                        *                  Register                                                   */

        struct
        {
            __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
                                        *   compares it on the condition of compare window B is selected.             */
            uint8_t             : 1;
            __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
        } ADCMPBNSR_b;
    };
    __IM uint8_t RESERVED11;

    union
    {
        __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
                                           *                  Setting Register                                           */

        struct
        {
            __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
                                           *   used to set the lower level of the window B.                              */
        } ADWINLLB_b;
    };

    union
    {
        __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
                                           *                  Setting Register                                           */

        struct
        {
            __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
                                           *   used to set the higher level of the window B.                             */
        } ADWINULB_b;
    };

    union
    {
        __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */

        struct
        {
            __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
                                        *   the comparative result of CH (AN000-AN027, temperature
                                        *   sensor, and internal reference voltage) made the object
                                        *   of window B relation condition.                                           */
            uint8_t : 7;
        } ADCMPBSR_b;
    };
    __IM uint8_t  RESERVED12;
    __IM uint16_t RESERVED13;

    union
    {
        __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF0_b;
    };

    union
    {
        __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF1_b;
    };

    union
    {
        __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF2_b;
    };

    union
    {
        __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF3_b;
    };

    union
    {
        __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF4_b;
    };

    union
    {
        __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF5_b;
    };

    union
    {
        __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF6_b;
    };

    union
    {
        __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF7_b;
    };

    union
    {
        __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF8_b;
    };

    union
    {
        __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF9_b;
    };

    union
    {
        __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF10_b;
    };

    union
    {
        __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF11_b;
    };

    union
    {
        __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF12_b;
    };

    union
    {
        __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF13_b;
    };

    union
    {
        __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF14_b;
    };

    union
    {
        __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */

        struct
        {
            __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
                                        *   registers that sequentially store all A/D converted values.
                                        *   The automatic clear function is not applied to these registers.           */
        } ADBUF15_b;
    };

    union
    {
        __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */

        struct
        {
            __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
            uint8_t             : 7;
        } ADBUFEN_b;
    };
    __IM uint8_t RESERVED14;

    union
    {
        __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */

        struct
        {
            __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
                                        *   data buffer to which the next A/D converted data is transferred.          */
            __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
            uint8_t             : 3;
        } ADBUFPTR_b;
    };
    __IM uint8_t  RESERVED15;
    __IM uint32_t RESERVED16[2];
    __IM uint8_t  RESERVED17;

    union
    {
        __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */

        struct
        {
            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
        } ADSSTRL_b;
    };

    union
    {
        __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */

        struct
        {
            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
        } ADSSTRT_b;
    };

    union
    {
        __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */

        struct
        {
            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
        } ADSSTRO_b;
    };

    union
    {
        __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */

        struct
        {
            __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
        } ADSSTR_b[16];
    };

    union
    {
        __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */

        struct
        {
            __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
            __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
            __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
            __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
            uint16_t             : 12;
        } ADANIM_b;
    };

    union
    {
        __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */

        struct
        {
            uint8_t              : 6;
            __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
            __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
        } ADCALEXE_b;
    };
    __IM uint8_t RESERVED18;

    union
    {
        __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
                                          *                  Register                                                   */

        struct
        {
            __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
            __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
            __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
            __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
            uint8_t                 : 2;
            __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
        } VREFAMPCNT_b;
    };
    __IM uint8_t  RESERVED19;
    __IM uint16_t RESERVED20;

    union
    {
        __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */

        struct
        {
            __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
        } ADRD_b;
    };

    union
    {
        __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */

        struct
        {
            __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
            uint8_t             : 6;
        } ADRST_b;
    };
    __IM uint8_t  RESERVED21;
    __IM uint32_t RESERVED22[41];

    union
    {
        __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */

        struct
        {
            __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
            __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
            __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
            __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
            __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
            __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
            __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
            __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
            __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
            __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
            __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
            __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
            __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
            __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
            __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
            __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
        } ADPGACR_b;
    };

    union
    {
        __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
                                          *                  Register 0                                                 */

        struct
        {
            __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
                                          *   b) when the shingle end is input and each PGA P000 is set.
                                          *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
                                          *   sets the gain magnification when the differential motion
                                          *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
            __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
                                          *   b) when the shingle end is input and each PGA P001 is set.
                                          *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
                                          *   sets the gain magnification when the differential motion
                                          *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
            __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
                                          *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
                                          *   each PGA P002 is set. When the differential motion is input,
                                          *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
                                          *   the differential motion is input by the combination with
                                          *   ADPGSDCR0.P002DG 1:0.                                                     */
            __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
                                          *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
                                          *   each PGA P003 is set. When the differential motion is input,
                                          *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
                                          *   the differential motion is input by the combination with
                                          *   ADPGSDCR0.P003DG 1:0.                                                     */
        } ADPGAGS0_b;
    };
    __IM uint32_t RESERVED23[3];

    union
    {
        __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
                                         *                  Input Control Register                                     */

        struct
        {
            __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
                                         *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
            uint16_t               : 1;
            __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
            __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
                                         *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
            uint16_t               : 1;
            __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
            __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
                                         *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
            uint16_t               : 1;
            __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
            __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
                                         *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
            uint16_t               : 1;
            __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
        } ADPGADCR0_b;
    };
    __IM uint16_t RESERVED24;

    union
    {
        __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
                                        *                  Input Bias Select Register 0                               */

        struct
        {
            __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
                                        *   SelectNOTE: This bit selects the input bias voltage value
                                        *   when differential inputs are used.                                        */
            uint8_t : 7;
        } ADPGADBS0_b;
    };

    union
    {
        __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
                                        *                  Input Bias Select Register 1                               */

        struct
        {
            __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
                                        *   This bit selects the input bias voltage value when differential
                                        *   inputs are used.                                                          */
            uint8_t : 7;
        } ADPGADBS1_b;
    };
    __IM uint16_t RESERVED25;
    __IM uint32_t RESERVED26[10];

    union
    {
        __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */

        struct
        {
            __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
            uint32_t              : 13;
            __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
            uint32_t              : 12;
        } ADREFMON_b;
    };
} R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */

/* =========================================================================================================================== */
/* ================                                          R_PSCU                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Peripheral Security Control Unit (R_PSCU)
 */

typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
{
    __IM uint32_t RESERVED;

    union
    {
        __IOM uint32_t PSARB;           /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */

        struct
        {
            __IOM uint32_t PSARB0  : 1; /*!< [0..0] UARTA and the MSTPCRB.MSTPB0 Bit Security Attribution              */
            __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
            __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
            __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
            __IOM uint32_t PSARB4  : 1; /*!< [4..4] I3C and the MSTPCRB.MSTPB4 Bit Security Attribution                */
            __IOM uint32_t PSARB5  : 1; /*!< [5..5] IrDA and the MSTPCRB.MSTPB5 Bit Security Attribution               */
            __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
            __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
            __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
            __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
            uint32_t               : 1;
            __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
            __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
            uint32_t               : 2;
            __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
                                         *   bit security attribution                                                  */
            __IM uint32_t  PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
            __IOM uint32_t PSARB17 : 1; /*!< [17..17] SPI1 and the MSTPCRB.MSTPB17 Bit Security Attribution            */
            __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
            __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
            uint32_t               : 2;
            __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
            __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
            __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
            __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
            __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
            __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
            __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
            __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
            __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
            __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
        } PSARB_b;
    };

    union
    {
        __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */

        struct
        {
            __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
            __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
            uint32_t               : 1;
            __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
            __IOM uint32_t PSARC4  : 1; /*!< [4..4] SLCDC and the MSTPCRB.MSTPC4 Bit Security Attribution              */
            uint32_t               : 3;
            __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
            uint32_t               : 3;
            __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
            __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
            uint32_t               : 6;
            __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
            uint32_t               : 6;
            __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
            uint32_t               : 3;
            __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
        } PSARC_b;
    };

    union
    {
        __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */

        struct
        {
            __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
            __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
            __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
            __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
            uint32_t               : 7;
            __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
            __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
            __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
            __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
            __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
            __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
            uint32_t               : 2;
            __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
            __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
            uint32_t               : 1;
            __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
            uint32_t               : 2;
            __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
            __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
            __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
            __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
            __IOM uint32_t PSARD29 : 1; /*!< [29..29] ACMPLP and the MSTPCRD.MSTPD29 Bit Security Attribution          */
            uint32_t               : 2;
        } PSARD_b;
    };

    union
    {
        __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */

        struct
        {
            __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
            __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
            __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
            uint32_t               : 11;
            __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
            __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
            uint32_t               : 6;
            __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
            __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
            __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
            __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
            __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
            __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
            __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
            __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
            __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
            __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
        } PSARE_b;
    };

    union
    {
        __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */

        struct
        {
            __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
            __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
            __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
            __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
            __IOM uint32_t MSSAR4 : 1; /*!< [4..4] The MSTPCRA.MSMSTPA16 Bit Security Attribution                     */
            uint32_t              : 27;
        } MSSAR_b;
    };

    union
    {
        __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
                                        *                  A                                                          */

        struct
        {
            uint32_t            : 15;
            __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
            uint32_t            : 8;
        } CFSAMONA_b;
    };

    union
    {
        __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
                                        *                  B                                                          */

        struct
        {
            uint32_t            : 10;
            __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
            uint32_t            : 8;
        } CFSAMONB_b;
    };

    union
    {
        __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */

        struct
        {
            uint32_t           : 10;
            __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
            uint32_t           : 16;
        } DFSAMON_b;
    };

    union
    {
        __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */

        struct
        {
            uint32_t           : 13;
            __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
            uint32_t           : 11;
        } SSAMONA_b;
    };

    union
    {
        __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */

        struct
        {
            uint32_t           : 10;
            __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
            uint32_t           : 11;
        } SSAMONB_b;
    };

    union
    {
        __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */

        struct
        {
            __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
            uint32_t             : 28;
        } DLMMON_b;
    };
} R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */

/* =========================================================================================================================== */
/* ================                                           R_BUS                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Bus Interface (R_BUS)
 */

typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
{
    __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
    __IM uint32_t        RESERVED[480];
    __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */

    union
    {
        __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */

        struct
        {
            __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
            __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
            __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
            __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
            __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
            __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
            __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
            __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
            __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
        } CSRECEN_b;
    };
    __IM uint16_t          RESERVED1;
    __IM uint32_t          RESERVED2[223];
    __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
    __IM uint32_t          RESERVED3[235];

    union
    {
        __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
        __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
    };
    __IM uint32_t RESERVED4[58];

    union
    {
        union
        {
            __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */

            struct
            {
                __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
                uint32_t            : 31;
            } BUSMABT_b;
        };
        __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
    };
    __IM uint32_t RESERVED5[46];

    union
    {
        __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
        __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
    };
    __IM uint32_t RESERVED6[33];

    union
    {
        __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */

        struct
        {
            __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
            uint32_t                : 2;
            __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
            uint32_t                : 12;
            __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
            uint32_t                : 15;
        } BUSDIVBYP_b;
    };
    __IM uint32_t RESERVED7[63];

    union
    {
        __IOM uint16_t BUSTHRPUT;      /*!< (@ 0x00001400) Graphic Bus Throughput Control Register                    */

        struct
        {
            __IOM uint16_t DIS : 1;    /*!< [0..0] Bandwidth Control Function                                         */
            uint16_t           : 15;
        } BUSTHRPUT_b;
    };
    __IM uint16_t            RESERVED8;
    __IM uint32_t            RESERVED9[255];
    __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
    __IM uint32_t            RESERVED10[16];

    union
    {
        __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
        __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
                                              *                  and Read/Write Status registers.                           */
    };
    __IM uint32_t RESERVED11[28];

    union
    {
        __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
        __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
    };
    __IM uint32_t           RESERVED12[16];
    __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
    __IM uint32_t           RESERVED13[5];
    __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
} R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */

/* =========================================================================================================================== */
/* ================                                           R_CAC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
 */

typedef struct                         /*!< (@ 0x40083600) R_CAC Structure                                            */
{
    union
    {
        __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */

        struct
        {
            __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
            uint8_t            : 7;
        } CACR0_b;
    };

    union
    {
        __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */

        struct
        {
            __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
            __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
            __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
            __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
        } CACR1_b;
    };

    union
    {
        __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */

        struct
        {
            __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
            __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
            __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
                                        *   Select                                                                    */
            __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
        } CACR2_b;
    };

    union
    {
        __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */

        struct
        {
            __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
            __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
            __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
            uint8_t              : 1;
            __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
            __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
            __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
            uint8_t              : 1;
        } CAICR_b;
    };

    union
    {
        __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */

        struct
        {
            __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
            __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
            __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
            uint8_t            : 5;
        } CASTR_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */

        struct
        {
            __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
                                         *   the upper-limit value of the frequency.                                   */
        } CAULVR_b;
    };

    union
    {
        __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */

        struct
        {
            __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
                                         *   the lower-limit value of the frequency.                                   */
        } CALLVR_b;
    };

    union
    {
        __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */

        struct
        {
            __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
                                         *   the counter value at the time a valid reference signal
                                         *   edge is input                                                             */
        } CACNTBR_b;
    };
} R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */

/* =========================================================================================================================== */
/* ================                                         R_CANFD0                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
 */

typedef struct                         /*!< (@ 0x400B0000) R_CANFD0 Structure                                         */
{
    __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
    __IM uint32_t           RESERVED;

    union
    {
        __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */

        struct
        {
            __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
            __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
            __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
            __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
            __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
            __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
            uint32_t             : 2;
            __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
            __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
            uint32_t             : 3;
            __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
        } CFDGCFG_b;
    };

    union
    {
        __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */

        struct
        {
            __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
            __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
            uint32_t               : 5;
            __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
            __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
            __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
            __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
            uint32_t               : 4;
            __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
            uint32_t               : 15;
        } CFDGCTR_b;
    };

    union
    {
        __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */

        struct
        {
            __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
            __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
            __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
            __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
            uint32_t               : 28;
        } CFDGSTS_b;
    };

    union
    {
        __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */

        struct
        {
            __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
            __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
            __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
            __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
            uint32_t             : 12;
            __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
            uint32_t             : 15;
        } CFDGERFL_b;
    };

    union
    {
        __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */

        struct
        {
            __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
            uint32_t         : 16;
        } CFDGTSC_b;
    };

    union
    {
        __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */

        struct
        {
            __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
            uint32_t              : 4;
            __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
            uint32_t              : 23;
        } CFDGAFLECTR_b;
    };

    union
    {
        __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
                                        *                  0                                                          */

        struct
        {
            __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
            uint32_t            : 7;
            __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
            uint32_t            : 7;
        } CFDGAFLCFG0_b;
    };

    union
    {
        __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */

        struct
        {
            __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
            __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
            uint32_t             : 21;
        } CFDRMNB_b;
    };

    union
    {
        __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */

        struct
        {
            __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
        } CFDRMND0_b;
    };

    union
    {
        __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
                                        *                  Register                                                   */

        struct
        {
            __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
        } CFDRMIEC_b;
    };

    union
    {
        __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */

        struct
        {
            __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
            __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
            uint32_t              : 2;
            __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
            uint32_t              : 1;
            __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
            uint32_t              : 1;
            __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
            __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
            uint32_t              : 16;
        } CFDRFCC_b[2];
    };

    union
    {
        __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */

        struct
        {
            __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
            __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
            __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
            __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
            uint32_t             : 4;
            __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
            uint32_t             : 16;
        } CFDRFSTS_b[2];
    };

    union
    {
        __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */

        struct
        {
            __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
            uint32_t           : 24;
        } CFDRFPCTR_b[2];
    };

    union
    {
        __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */

        struct
        {
            __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
            __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
            __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
            uint32_t              : 1;
            __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
            uint32_t              : 1;
            __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
            __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
            __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
            __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
            __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
            __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
            __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
            __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
        } CFDCFCC_b[1];
    };

    union
    {
        __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */

        struct
        {
            __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
            __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
            __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
            __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
            __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
            uint32_t              : 3;
            __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
            uint32_t              : 16;
        } CFDCFSTS_b[1];
    };

    union
    {
        __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */

        struct
        {
            __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
            uint32_t           : 24;
        } CFDCFPCTR_b[1];
    };

    union
    {
        __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */

        struct
        {
            __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
            uint32_t             : 6;
            __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
            uint32_t             : 23;
        } CFDFESTS_b;
    };

    union
    {
        __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */

        struct
        {
            __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
            uint32_t             : 6;
            __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
            uint32_t             : 23;
        } CFDFFSTS_b;
    };

    union
    {
        __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */

        struct
        {
            __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
            uint32_t             : 6;
            __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
            uint32_t             : 23;
        } CFDFMSTS_b;
    };

    union
    {
        __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */

        struct
        {
            __IM uint32_t RFXIF : 2;   /*!< [1..0] RX FIFO[x] Interrupt Flag Status                                   */
            uint32_t            : 30;
        } CFDRFISTS_b;
    };

    union
    {
        __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */

        struct
        {
            __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
            __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
            __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
            uint8_t             : 5;
        } CFDTMC_b[4];
    };

    union
    {
        __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */

        struct
        {
            __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
            __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
            __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
            __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
            uint8_t              : 3;
        } CFDTMSTS_b[4];
    };

    union
    {
        __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
                                            *                  Register                                                   */

        struct
        {
            __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
            uint32_t                  : 28;
        } CFDTMTRSTS_b[1];
    };

    union
    {
        __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
                                             *                  Status Register                                            */

        struct
        {
            __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
            uint32_t                   : 28;
        } CFDTMTARSTS_b[1];
    };

    union
    {
        __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
                                            *                  Register                                                   */

        struct
        {
            __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
            uint32_t                  : 28;
        } CFDTMTCSTS_b[1];
    };

    union
    {
        __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */

        struct
        {
            __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
            uint32_t                  : 28;
        } CFDTMTASTS_b[1];
    };

    union
    {
        __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
                                        *                  Register                                                   */

        struct
        {
            __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
            uint32_t             : 28;
        } CFDTMIEC_b[1];
    };

    union
    {
        __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */

        struct
        {
            __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
            uint32_t               : 4;
            __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
            uint32_t               : 1;
            __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
            __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
            uint32_t               : 22;
        } CFDTXQCC0_b[1];
    };

    union
    {
        __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */

        struct
        {
            __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
            __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
            __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
            uint32_t               : 5;
            __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
            uint32_t               : 18;
        } CFDTXQSTS0_b[1];
    };

    union
    {
        __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */

        struct
        {
            __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
            uint32_t            : 24;
        } CFDTXQPCTR0_b[1];
    };

    union
    {
        __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */

        struct
        {
            __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
            uint32_t              : 7;
            __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
            __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
            __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
            uint32_t              : 21;
        } CFDTHLCC_b[1];
    };

    union
    {
        __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */

        struct
        {
            __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
            __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
            __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
            __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
            uint32_t              : 4;
            __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
            uint32_t              : 18;
        } CFDTHLSTS_b[1];
    };

    union
    {
        __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */

        struct
        {
            __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
            uint32_t            : 24;
        } CFDTHLPCTR_b[1];
    };

    union
    {
        __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */

        struct
        {
            __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
            __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
            __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
            __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
            __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
            uint32_t             : 27;
        } CFDGTINTSTS0_b;
    };

    union
    {
        __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */

        struct
        {
            uint32_t             : 16;
            __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
            uint32_t             : 6;
        } CFDGTSTCFG_b;
    };

    union
    {
        __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */

        struct
        {
            uint32_t            : 2;
            __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
            uint32_t            : 29;
        } CFDGTSTCTR_b;
    };

    union
    {
        __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */

        struct
        {
            __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
            uint32_t              : 7;
            __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
            uint32_t              : 22;
        } CFDGFDCFG_b;
    };
    __IM uint32_t RESERVED1;

    union
    {
        __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */

        struct
        {
            __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
            uint32_t           : 16;
        } CFDGLOCKK_b;
    };
    __IM uint32_t RESERVED2;

    union
    {
        __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */

        struct
        {
            __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
            uint32_t           : 27;
        } CFDGAFLIGNENT_b;
    };

    union
    {
        __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */

        struct
        {
            __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
            uint32_t            : 7;
            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
            uint32_t            : 16;
        } CFDGAFLIGNCTR_b;
    };

    union
    {
        __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */

        struct
        {
            __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
            __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
            uint32_t               : 6;
            __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
            uint32_t               : 23;
        } CFDCDTCT_b;
    };

    union
    {
        __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */

        struct
        {
            __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
            __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
            uint32_t                : 6;
            __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
                                          *   0                                                                         */
            uint32_t : 23;
        } CFDCDTSTS_b;
    };
    __IM uint32_t RESERVED3[2];

    union
    {
        __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */

        struct
        {
            __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
            uint32_t            : 7;
            __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
            uint32_t            : 16;
        } CFDGRSTC_b;
    };
    __IM uint32_t              RESERVED4[9];
    __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
    __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
    __IM uint32_t              RESERVED5[24];

    union
    {
        __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */

        struct
        {
            __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
        } CFDRPGACC_b[64];
    };
    __IM uint32_t             RESERVED6[104];
    __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
    __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
    __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
    __IM uint32_t             RESERVED7[3];
    __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
    __IM uint32_t             RESERVED8[118];
    __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
} R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */

/* =========================================================================================================================== */
/* ================                                           R_CRC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
 */

typedef struct                         /*!< (@ 0x40108000) R_CRC Structure                                            */
{
    union
    {
        __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */

        struct
        {
            __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
            uint8_t              : 3;
            __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
            __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
        } CRCCR0_b;
    };

    union
    {
        __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */

        struct
        {
            uint8_t              : 6;
            __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
            __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
        } CRCCR1_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        union
        {
            __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */

            struct
            {
                __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
            } CRCDIR_b;
        };

        union
        {
            __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */

            struct
            {
                __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
                                              *   )                                                                         */
            } CRCDIR_BY_b;
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */

            struct
            {
                __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
            } CRCDOR_b;
        };

        union
        {
            __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */

            struct
            {
                __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
                                                *   )                                                                         */
            } CRCDOR_HA_b;
        };

        union
        {
            __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */

            struct
            {
                __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
            } CRCDOR_BY_b;
        };
    };

    union
    {
        __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */

        struct
        {
            __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
            uint16_t             : 2;
        } CRCSAR_b;
    };
    __IM uint16_t RESERVED1;
} R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_CTSU2                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Capacitive Touch Sensing Unit (R_CTSU2)
 */

typedef struct                         /*!< (@ 0x400D0000) R_CTSU2 Structure                                          */
{
    union
    {
        union
        {
            __IOM uint32_t CTSUCRA;        /*!< (@ 0x00000000) CTSU Control Register A                                    */

            struct
            {
                __IOM uint32_t STRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
                __IOM uint32_t CAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
                __IOM uint32_t SNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
                __IOM uint32_t CFCON  : 1; /*!< [3..3] CTSU CFC Power on Control                                          */
                __OM uint32_t  INIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
                __IOM uint32_t PUMPON : 1; /*!< [5..5] CTSU Boost Circuit Control                                         */
                __IOM uint32_t TXVSEL : 2; /*!< [7..6] CTSU Transmission Power Supply Selection                           */
                __IOM uint32_t PON    : 1; /*!< [8..8] CTSU Power On Control                                              */
                __IOM uint32_t CSW    : 1; /*!< [9..9] TSCAP Pin Enable                                                   */
                __IOM uint32_t ATUNE0 : 1; /*!< [10..10] CTSU Power Supply Operating Mode Setting                         */
                __IOM uint32_t ATUNE1 : 1; /*!< [11..11] CTSU Current Range Adjustment                                    */
                __IOM uint32_t CLK    : 2; /*!< [13..12] CTSU Operating Clock Select                                      */
                __IOM uint32_t MD0    : 1; /*!< [14..14] CTSU Measurement Mode Select 0                                   */
                __IOM uint32_t MD1    : 1; /*!< [15..15] CTSU Measurement Mode Select 1                                   */
                __IOM uint32_t MD2    : 1; /*!< [16..16] CTSU Measurement Mode Select 2                                   */
                __IOM uint32_t ATUNE2 : 1; /*!< [17..17] CTSU Current Range Adjustment                                    */
                __IOM uint32_t LOAD   : 2; /*!< [19..18] CTSU Load Control During Measurement                             */
                __IOM uint32_t POSEL  : 2; /*!< [21..20] CTSU Non-measured Channel Output Select                          */
                __IOM uint32_t SDPSEL : 1; /*!< [22..22] CTSU Sensor Drive Pulse Select                                   */
                __IOM uint32_t PCSEL  : 1; /*!< [23..23] CTSU Boost Circuit Clock Select                                  */
                __IOM uint32_t STCLK  : 6; /*!< [29..24] CTSU STCLK Select                                                */
                __IOM uint32_t DCMODE : 1; /*!< [30..30] CTSU Current Measurement Mode Select                             */
                __IOM uint32_t DCBACK : 1; /*!< [31..31] CTSU Current Measurement Feedback Select                         */
            } CTSUCRA_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUCRAL;   /*!< (@ 0x00000000) CTSU Control Register A                                    */

                struct
                {
                    __IOM uint8_t CTSUCR0; /*!< (@ 0x00000000) CTSU Control Register A                                    */
                    __IOM uint8_t CTSUCR1; /*!< (@ 0x00000001) CTSU Control Register A                                    */
                };
            };

            union
            {
                __IOM uint16_t CTSUCRAH;   /*!< (@ 0x00000002) CTSU Control Register A                                    */

                struct
                {
                    __IOM uint8_t CTSUCR2; /*!< (@ 0x00000002) CTSU Control Register A                                    */
                    __IOM uint8_t CTSUCR3; /*!< (@ 0x00000003) CTSU Control Register A                                    */
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCRB;         /*!< (@ 0x00000004) CTSU Control Register B                                    */

            struct
            {
                __IOM uint32_t PRRATIO : 4; /*!< [3..0] Frequency of Drive Pulse Phase Control                             */
                __IOM uint32_t PRMODE  : 2; /*!< [5..4] Phase Control Period                                               */
                __IOM uint32_t SOFF    : 1; /*!< [6..6] High-Pass Noise Reduction Function Disable                         */
                __IOM uint32_t PROFF   : 1; /*!< [7..7] Drive Pulse Phase Control                                          */
                __IOM uint32_t SST     : 8; /*!< [15..8] Wait Time Sensor Stabilization                                    */
                uint32_t               : 8;
                __IOM uint32_t SSMOD   : 3; /*!< [26..24] Spread Spectrum Modulation Frequency                             */
                uint32_t               : 1;
                __IOM uint32_t SSCNT   : 2; /*!< [29..28] Adjusting the SUCLK frequency                                    */
                uint32_t               : 2;
            } CTSUCRB_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUCRBL;     /*!< (@ 0x00000004) CTSU Control Register B                                    */

                struct
                {
                    __IOM uint8_t CTSUSDPRS; /*!< (@ 0x00000004) CTSU Control Register B                                    */
                    __IOM uint8_t CTSUSST;   /*!< (@ 0x00000005) CTSU Control Register B                                    */
                };
            };

            union
            {
                __IOM uint16_t CTSUCRBH; /*!< (@ 0x00000006) CTSU Control Register B                                    */

                struct
                {
                    __IM uint8_t  RESERVED;
                    __IOM uint8_t CTSUDCLKC; /*!< (@ 0x00000007) CTSU Control Register B                                    */
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUMCH;      /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */

            struct
            {
                __IOM uint32_t MCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0                                         */
                uint32_t            : 2;
                __IOM uint32_t MCH1 : 6; /*!< [13..8] CTSU Measurement Channel 1                                        */
                uint32_t            : 2;
                __IOM uint32_t MCA0 : 1; /*!< [16..16] CTSU Multiple Valid Clock Control                                */
                __IOM uint32_t MCA1 : 1; /*!< [17..17] CTSU Multiple Valid Clock Control                                */
                __IOM uint32_t MCA2 : 1; /*!< [18..18] CTSU Multiple Valid Clock Control                                */
                __IOM uint32_t MCA3 : 1; /*!< [19..19] CTSU Multiple Valid Clock Control                                */
                uint32_t            : 12;
            } CTSUMCH_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUMCHL;    /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */

                struct
                {
                    __IOM uint8_t CTSUMCH0; /*!< (@ 0x00000008) CTSU Measurement Channel Register                          */
                    __IOM uint8_t CTSUMCH1; /*!< (@ 0x00000009) CTSU Measurement Channel Register                          */
                };
            };

            union
            {
                __IOM uint16_t CTSUMCHH; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
                __IOM uint8_t  CTSUMFAF; /*!< (@ 0x0000000A) CTSU Measurement Channel Register                          */
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCHACA;      /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */

            struct
            {
                __IOM uint32_t CHAC00 : 1; /*!< [0..0] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC01 : 1; /*!< [1..1] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC02 : 1; /*!< [2..2] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC03 : 1; /*!< [3..3] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC04 : 1; /*!< [4..4] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC05 : 1; /*!< [5..5] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC06 : 1; /*!< [6..6] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC07 : 1; /*!< [7..7] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC08 : 1; /*!< [8..8] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC09 : 1; /*!< [9..9] CTSU Channel Enable Control A                                      */
                __IOM uint32_t CHAC10 : 1; /*!< [10..10] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC11 : 1; /*!< [11..11] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC12 : 1; /*!< [12..12] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC13 : 1; /*!< [13..13] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC14 : 1; /*!< [14..14] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC15 : 1; /*!< [15..15] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC16 : 1; /*!< [16..16] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC17 : 1; /*!< [17..17] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC18 : 1; /*!< [18..18] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC19 : 1; /*!< [19..19] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC20 : 1; /*!< [20..20] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC21 : 1; /*!< [21..21] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC22 : 1; /*!< [22..22] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC23 : 1; /*!< [23..23] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC24 : 1; /*!< [24..24] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC25 : 1; /*!< [25..25] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC26 : 1; /*!< [26..26] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC27 : 1; /*!< [27..27] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC28 : 1; /*!< [28..28] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC29 : 1; /*!< [29..29] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC30 : 1; /*!< [30..30] CTSU Channel Enable Control A                                    */
                __IOM uint32_t CHAC31 : 1; /*!< [31..31] CTSU Channel Enable Control A                                    */
            } CTSUCHACA_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUCHACAL;   /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */

                struct
                {
                    __IOM uint8_t CTSUCHAC0; /*!< (@ 0x0000000C) CTSU Channel Enable Control Register A                     */
                    __IOM uint8_t CTSUCHAC1; /*!< (@ 0x0000000D) CTSU Channel Enable Control Register A                     */
                };
            };

            union
            {
                __IOM uint16_t CTSUCHACAH;   /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */

                struct
                {
                    __IOM uint8_t CTSUCHAC2; /*!< (@ 0x0000000E) CTSU Channel Enable Control Register A                     */
                    __IOM uint8_t CTSUCHAC3; /*!< (@ 0x0000000F) CTSU Channel Enable Control Register A                     */
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCHACB;      /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */

            struct
            {
                __IOM uint32_t CHAC32 : 1; /*!< [0..0] CTSU Channel Enable Control B                                      */
                __IOM uint32_t CHAC33 : 1; /*!< [1..1] CTSU Channel Enable Control B                                      */
                __IOM uint32_t CHAC34 : 1; /*!< [2..2] CTSU Channel Enable Control B                                      */
                __IOM uint32_t CHAC35 : 1; /*!< [3..3] CTSU Channel Enable Control B                                      */
                uint32_t              : 28;
            } CTSUCHACB_b;
        };
        __IOM uint16_t CTSUCHACBL;         /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
        __IOM uint8_t  CTSUCHAC4;          /*!< (@ 0x00000010) CTSU Channel Enable Control Register B                     */
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCHTRCA;      /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
                                             *                  A                                                          */

            struct
            {
                __IOM uint32_t CHTRC   : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC01 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC02 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC03 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC04 : 1; /*!< [4..4] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC05 : 1; /*!< [5..5] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC06 : 1; /*!< [6..6] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC07 : 1; /*!< [7..7] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC08 : 1; /*!< [8..8] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC09 : 1; /*!< [9..9] CTSU Channel Transmit/Receive Control A                            */
                __IOM uint32_t CHTRC10 : 1; /*!< [10..10] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC11 : 1; /*!< [11..11] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC12 : 1; /*!< [12..12] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC13 : 1; /*!< [13..13] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC14 : 1; /*!< [14..14] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC15 : 1; /*!< [15..15] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC16 : 1; /*!< [16..16] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC17 : 1; /*!< [17..17] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC18 : 1; /*!< [18..18] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC19 : 1; /*!< [19..19] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC20 : 1; /*!< [20..20] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC21 : 1; /*!< [21..21] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC22 : 1; /*!< [22..22] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC23 : 1; /*!< [23..23] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC24 : 1; /*!< [24..24] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC25 : 1; /*!< [25..25] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC26 : 1; /*!< [26..26] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC27 : 1; /*!< [27..27] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC28 : 1; /*!< [28..28] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC29 : 1; /*!< [29..29] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC30 : 1; /*!< [30..30] CTSU Channel Transmit/Receive Control A                          */
                __IOM uint32_t CHTRC31 : 1; /*!< [31..31] CTSU Channel Transmit/Receive Control A                          */
            } CTSUCHTRCA_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUCHTRCAL;   /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */

                struct
                {
                    __IOM uint8_t CTSUCHTRC0; /*!< (@ 0x00000014) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */
                    __IOM uint8_t CTSUCHTRC1; /*!< (@ 0x00000015) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */
                };
            };

            union
            {
                __IOM uint16_t CTSUCHTRCAH;   /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */

                struct
                {
                    __IOM uint8_t CTSUCHTRC2; /*!< (@ 0x00000016) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */
                    __IOM uint8_t CTSUCHTRC3; /*!< (@ 0x00000017) CTSU Channel Transmit/Receive Control Register
                                               *                  A                                                          */
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCHTRCB;      /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
                                             *                  B                                                          */

            struct
            {
                __IOM uint32_t CHTRC32 : 1; /*!< [0..0] CTSU Channel Transmit/Receive Control B                            */
                __IOM uint32_t CHTRC33 : 1; /*!< [1..1] CTSU Channel Transmit/Receive Control B                            */
                __IOM uint32_t CHTRC34 : 1; /*!< [2..2] CTSU Channel Transmit/Receive Control B                            */
                __IOM uint32_t CHTRC35 : 1; /*!< [3..3] CTSU Channel Transmit/Receive Control B                            */
                uint32_t               : 28;
            } CTSUCHTRCB_b;
        };
        __IOM uint16_t CTSUCHTRCBL;         /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
                                             *                  B                                                          */
        __IOM uint8_t CTSUCHTRC4;           /*!< (@ 0x00000018) CTSU Channel Transmit/Receive Control Register
                                             *                  B                                                          */
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUSR;          /*!< (@ 0x0000001C) CTSU Status Register                                       */

            struct
            {
                __IOM uint32_t MFC     : 2; /*!< [1..0] CTSU Multi-clock Counter                                           */
                uint32_t               : 3;
                __OM uint32_t ICOMPRST : 1; /*!< [5..5] CTSU CTSUICOMP1 Flag Reset                                         */
                __IM uint32_t ICOMP1   : 1; /*!< [6..6] CTSU Sense Current Error Monitor                                   */
                __IM uint32_t ICOMP0   : 1; /*!< [7..7] TSCAP Voltage Error Monitor                                        */
                __IM uint32_t STC      : 3; /*!< [10..8] CTSU Measurement Status Counter                                   */
                uint32_t               : 1;
                __IM uint32_t  DTSR    : 1; /*!< [12..12] CTSU Data Transfer Status Flag                                   */
                __IOM uint32_t SENSOVF : 1; /*!< [13..13] CTSU Sensor Counter Overflow Flag                                */
                __IOM uint32_t SUOVF   : 1; /*!< [14..14] CTSU SUCLK Counter Overflow Flag                                 */
                __IM uint32_t  PS      : 1; /*!< [15..15] CTSU Mutual Capacitance Status Flag                              */
                __IOM uint32_t CFCRDCH : 6; /*!< [21..16] CTSU CFC Read Channel Select                                     */
                uint32_t               : 10;
            } CTSUSR_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUSRL;    /*!< (@ 0x0000001C) CTSU Status Register                                       */

                struct
                {
                    __IOM uint8_t CTSUSR0; /*!< (@ 0x0000001C) CTSU Status Register                                       */
                    __IOM uint8_t CTSUST;  /*!< (@ 0x0000001D) CTSU Status Register                                       */
                };
            };

            union
            {
                __IOM uint16_t CTSUSRH; /*!< (@ 0x0000001E) CTSU Status Register                                       */
                __IOM uint8_t  CTSUSR2; /*!< (@ 0x0000001E) CTSU Status Register                                       */
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUSO;         /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */

            struct
            {
                __IOM uint32_t SO    : 10; /*!< [9..0] CTSU Sensor Offset Adjustment                                      */
                __IOM uint32_t SNUM  : 8;  /*!< [17..10] CTSU Measurement Count Setting                                   */
                uint32_t             : 2;
                __IOM uint32_t SSDIV : 4;  /*!< [23..20] Spread Spectrum Frequency                                        */
                __IOM uint32_t SDPA  : 8;  /*!< [31..24] CTSU Base Clock Setting                                          */
            } CTSUSO_b;
        };

        struct
        {
            __IOM uint16_t CTSUSO0;    /*!< (@ 0x00000020) CTSU Sensor Offset Register                                */
            __IOM uint16_t CTSUSO1;    /*!< (@ 0x00000022) CTSU Sensor Offset Register                                */
        };
    };

    union
    {
        union
        {
            __IM uint32_t CTSUSCNT;         /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */

            struct
            {
                __IM uint32_t SENSCNT : 16; /*!< [15..0] CTSU Sensor Counter                                               */
                __IM uint32_t SUCKCNT : 16; /*!< [31..16] CTSU SUCLK Counter                                               */
            } CTSUSCNT_b;
        };
        __IM uint16_t CTSUSC;               /*!< (@ 0x00000024) CTSU Sensor Counter Register                               */
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUCALIB;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */

            struct
            {
                uint32_t                : 2;
                __IOM uint32_t TSOD     : 1; /*!< [2..2] TS Pins Fixed Output                                               */
                __IOM uint32_t DRV      : 1; /*!< [3..3] Power Supply Calibration Select                                    */
                __IOM uint32_t CLKSEL   : 2; /*!< [5..4] Observation Clock Select                                           */
                __IOM uint32_t SUCLKEN  : 1; /*!< [6..6] SUCLK Forced Oscillation Control                                   */
                __IOM uint32_t TSOC     : 1; /*!< [7..7] Switched Capacitor Operation Calibration Select Bit                */
                __IOM uint32_t CNTRDSEL : 1; /*!< [8..8] Read Count Select of Sensor Counter                                */
                __IOM uint32_t IOC      : 1; /*!< [9..9] TS Pin Fixed Output Value Set                                      */
                __IOM uint32_t CFCRDMD  : 1; /*!< [10..10] CFC Counter Read Mode Select                                     */
                __IOM uint32_t DCOFF    : 1; /*!< [11..11] Down Converter Control                                           */
                __IOM uint32_t IOCSEL   : 1; /*!< [12..12] TS Pins Fixed Output Select                                      */
                uint32_t                : 3;
                __IOM uint32_t CFCSEL   : 6; /*!< [21..16] Observation CFC Clock Select                                     */
                __IOM uint32_t CFCMODE  : 1; /*!< [22..22] CFC Oscillator Calibration Mode Select                           */
                uint32_t                : 1;
                __IOM uint32_t DACMSEL  : 1; /*!< [24..24] Current Offset DAC Current Matrix Calibration Select             */
                __IOM uint32_t DACCARRY : 1; /*!< [25..25] Offset Current Adjustment for Calibration                        */
                __IOM uint32_t SUMSEL   : 1; /*!< [26..26] Current Control Oscillator Input Current Matrix Calibration
                                              *   Select                                                                    */
                __IOM uint32_t SUCARRY : 1;  /*!< [27..27] Current Control Oscillator Input Current Adjustment
                                              *   for SUCLK                                                                 */
                __IOM uint32_t DACCLK : 1;   /*!< [28..28] Modulation Clock Select for Offset Current Circuits              */
                __IOM uint32_t CCOCLK : 1;   /*!< [29..29] Modulation Clock Select for Current Controlled Oscillator
                                              *   Input Current of SUCLK                                                    */
                __IOM uint32_t CCOCALIB : 1; /*!< [30..30] Calibration Selection of Current Controlled Oscillator
                                              *   for Measurement                                                           */
                __IOM uint32_t TXREV : 1;    /*!< [31..31] Transmit Pin Inverted Output                                     */
            } CTSUCALIB_b;
        };

        struct
        {
            __IOM uint16_t CTSUDBGR0;  /*!< (@ 0x00000028) CTSU Calibration Register                                  */
            __IOM uint16_t CTSUDBGR1;  /*!< (@ 0x0000002A) CTSU Calibration Register                                  */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUSUCLKA;       /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */

            struct
            {
                __IOM uint32_t SUADJ0   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
                __IOM uint32_t SUMULTI0 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
                __IOM uint32_t SUADJ1   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
                __IOM uint32_t SUMULTI1 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
            } CTSUSUCLKA_b;
        };

        struct
        {
            __IOM uint16_t CTSUSUCLK0; /*!< (@ 0x0000002C) CTSU Sensor Unit Clock Control Register A                  */
            __IOM uint16_t CTSUSUCLK1; /*!< (@ 0x0000002E) CTSU Sensor Unit Clock Control Register A                  */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUSUCLKB;       /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */

            struct
            {
                __IOM uint32_t SUADJ2   : 8; /*!< [7..0] CTSU SUCLK Frequency Adjustment                                    */
                __IOM uint32_t SUMULTI2 : 8; /*!< [15..8] CTSU SUCLK Multiplier Rate Setting                                */
                __IOM uint32_t SUADJ3   : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
                __IOM uint32_t SUMULTI3 : 8; /*!< [31..24] CTSU SUCLK Multiplier Rate Setting                               */
            } CTSUSUCLKB_b;
        };

        struct
        {
            __IOM uint16_t CTSUSUCLK2; /*!< (@ 0x00000030) CTSU Sensor Unit Clock Control Register B                  */
            __IOM uint16_t CTSUSUCLK3; /*!< (@ 0x00000032) CTSU Sensor Unit Clock Control Register B                  */
        };
    };

    union
    {
        union
        {
            __IM uint32_t CTSUCFCCNT;      /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */

            struct
            {
                __IM uint32_t CFCCNT : 16; /*!< [15..0] CTSU CFC Counter                                                  */
                uint32_t             : 16;
            } CTSUCFCCNT_b;
        };
        __IM uint16_t CTSUCFCCNTL;         /*!< (@ 0x00000034) CTSU CFC Counter Register                                  */
    };
    __IM uint32_t RESERVED1[2];

    union
    {
        union
        {
            __IOM uint32_t CTSUOPT;          /*!< (@ 0x00000040) CTSU Option Setting Register                               */

            struct
            {
                __IOM uint32_t CCOCFEN  : 1; /*!< [0..0] CCO Characteristics Correction Function Enable                     */
                __IOM uint32_t MCACEFN  : 1; /*!< [1..1] Multi-clock Correction Function Enable                             */
                __IOM uint32_t MAJIRIMD : 1; /*!< [2..2] Majority Mode                                                      */
                uint32_t                : 1;
                __IOM uint32_t DTCLESS  : 1; /*!< [4..4] Data Transfer Request Disable                                      */
                __IOM uint32_t MTUCFEN  : 1; /*!< [5..5] 5 MTUCFEN Mutual Capacitance Calculation Enable                    */
                uint32_t                : 2;
                __IOM uint32_t AJFEN    : 1; /*!< [8..8] Automatic Judgment Function Enable                                 */
                __IOM uint32_t AJINTC   : 1; /*!< [9..9] Automatic Judgment Interrupt Control                               */
                uint32_t                : 6;
                __IOM uint32_t SCACTB   : 4; /*!< [19..16] Sensor Counter Automatic Correction Table Number Setting         */
                uint32_t                : 12;
            } CTSUOPT_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUOPTL; /*!< (@ 0x00000040) CTSU Option Setting Register                               */

                struct
                {
                    union
                    {
                        __IOM uint8_t AC;               /*!< (@ 0x00000040) CTSU Option Setting Register                               */

                        struct
                        {
                            __IOM uint8_t CCOCFEN  : 1; /*!< [0..0] CCO Characteristics Correction Function Enable                     */
                            __IOM uint8_t MCACEFN  : 1; /*!< [1..1] Multi-clock Correction Function Enable                             */
                            __IOM uint8_t MAJIRIMD : 1; /*!< [2..2] Majority Mode                                                      */
                            uint8_t                : 1;
                            __IOM uint8_t DTCLESS  : 1; /*!< [4..4] Data Transfer Request Disable                                      */
                            __IOM uint8_t MTUCFEN  : 1; /*!< [5..5] Mutual Capacitance Calculation Enable                              */
                            uint8_t                : 2;
                        } AC_b;
                    };

                    union
                    {
                        __IOM uint8_t AJ;             /*!< (@ 0x00000041) CTSU Option Setting Register                               */

                        struct
                        {
                            __IOM uint8_t AJFEN  : 1; /*!< [0..0] Automatic Judgment Function Enable                                 */
                            __IOM uint8_t AJINTC : 1; /*!< [1..1] Automatic Judgment Interrupt Control                               */
                            uint8_t              : 6;
                        } AJ_b;
                    };
                };
            };

            union
            {
                __IOM uint16_t CTSUOPTH;          /*!< (@ 0x00000042) CTSU Option Setting Register                               */

                union
                {
                    __IOM uint8_t ACTB;           /*!< (@ 0x00000042) CTSU Option Setting Register                               */

                    struct
                    {
                        __IOM uint8_t SCACTB : 4; /*!< [3..0] Sensor Counter Automatic Correction Table Number Setting           */
                        uint8_t              : 4;
                    } ACTB_b;
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUSCNTACT;          /*!< (@ 0x00000044) CTSU Sensor Counter Automatic Correction Table
                                                  *                  Access Register                                            */

            struct
            {
                __IOM uint32_t SCNTACCOEFF : 16; /*!< [15..0] Sensor Counter Correction Coefficient Setting                     */
                __IOM uint32_t SCNTACCOUNT : 16; /*!< [31..16] Set the measurement value to be compared                         */
            } CTSUSCNTACT_b;
        };

        struct
        {
            __IOM uint16_t CTSUSCNTACTL; /*!< (@ 0x00000044) CTSU Option Setting Register                               */
            __IOM uint16_t CTSUSCNTACTH; /*!< (@ 0x00000046) CTSU Option Setting Register                               */
        };
    };
    __IM uint32_t RESERVED2;

    union
    {
        union
        {
            __IOM uint32_t CTSUMACT1;            /*!< (@ 0x0000004C) Multi-Clock Automatic Correction Table Access
                                                  *                  Register                                                   */

            struct
            {
                __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
                uint32_t                   : 6;
                __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
            } CTSUMACT1_b;
        };

        struct
        {
            __IOM uint16_t CTSUMACT1L; /*!< (@ 0x0000004C) CTSU Option Setting Register                               */
            __IOM uint16_t CTSUMACT1H; /*!< (@ 0x0000004E) CTSU Option Setting Register                               */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUMACT2;            /*!< (@ 0x00000050) Multi-Clock Automatic Correction Table Access
                                                  *                  Register                                                   */

            struct
            {
                __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
                uint32_t                   : 6;
                __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
            } CTSUMACT2_b;
        };

        struct
        {
            __IOM uint16_t CTSUMACT2L; /*!< (@ 0x00000050) CTSU Option Setting Register                               */
            __IOM uint16_t CTSUMACT2H; /*!< (@ 0x00000052) CTSU Option Setting Register                               */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUMACT3;            /*!< (@ 0x00000054) Multi-Clock Automatic Correction Table Access
                                                  *                  Register                                                   */

            struct
            {
                __IOM uint32_t SO          : 10; /*!< [9..0] Sensor offset adjustment bits for multi-clock                      */
                uint32_t                   : 6;
                __IOM uint32_t OFFSETCOEFF : 16; /*!< [31..16] Offset coefficient bits for multi-clock                          */
            } CTSUMACT3_b;
        };

        struct
        {
            __IOM uint16_t CTSUMACT3L; /*!< (@ 0x00000054) CTSU Option Setting Register                               */
            __IOM uint16_t CTSUMACT3H; /*!< (@ 0x00000056) CTSU Option Setting Register                               */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJCR;       /*!< (@ 0x00000058) CTSU Automatic Judgment Control Registe                    */

            struct
            {
                __IOM uint32_t TLOT   : 8; /*!< [7..0] Non-Touch Judgment Criterion Setting                               */
                __IOM uint32_t THOT   : 8; /*!< [15..8] Touch Judgment Criterion Setting                                  */
                __IOM uint32_t BLINI  : 1; /*!< [16..16] Baseline Initialization                                          */
                uint32_t              : 3;
                __IOM uint32_t JC     : 2; /*!< [21..20] Judgment Condition Setting                                       */
                uint32_t              : 2;
                __IOM uint32_t AJMMAT : 4; /*!< [27..24] Measured Value Moving Average Number Setting                     */
                __IOM uint32_t AJBMAT : 4; /*!< [31..28] Baseline Average Number Setting                                  */
            } CTSUAJCR_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t CTSUAJCRL; /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register                   */

                struct
                {
                    union
                    {
                        __IOM uint8_t AJCR0;        /*!< (@ 0x00000058) CTSU Automatic Judgment Control Register                   */

                        struct
                        {
                            __IOM uint8_t TLOT : 8; /*!< [7..0] Non-Touch Judgment Criterion Setting                               */
                        } AJCR0_b;
                    };

                    union
                    {
                        __IOM uint8_t AJCR1;        /*!< (@ 0x00000059) CTSU Automatic Judgment Control Register                   */

                        struct
                        {
                            __IOM uint8_t THOT : 8; /*!< [7..0] Touch Judgment Criterion Setting                                   */
                        } AJCR1_b;
                    };
                };
            };

            union
            {
                __IOM uint16_t CTSUAJCRH; /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register                   */

                struct
                {
                    union
                    {
                        __IOM uint8_t AJCR2;         /*!< (@ 0x0000005A) CTSU Automatic Judgment Control Register                   */

                        struct
                        {
                            __IOM uint8_t BLINI : 1; /*!< [0..0] Baseline Initialization                                            */
                            uint8_t             : 3;
                            __IOM uint8_t JC    : 2; /*!< [5..4] Judgment Condition Setting                                         */
                            uint8_t             : 2;
                        } AJCR2_b;
                    };

                    union
                    {
                        __IOM uint8_t AJCR3;          /*!< (@ 0x0000005B) CTSU Automatic Judgment Control Register                   */

                        struct
                        {
                            __IOM uint8_t AJMMAT : 4; /*!< [3..0] Measured Value Moving Average Number Setting                       */
                            __IOM uint8_t AJBMAT : 4; /*!< [7..4] Baseline Average Number Setting                                    */
                        } AJCR3_b;
                    };
                };
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJTHR;      /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register                   */

            struct
            {
                __IOM uint32_t AJTHL : 16; /*!< [15..0] Lower Threshold Setting                                           */
                __IOM uint32_t AJTHH : 16; /*!< [31..16] Upper Threshold Setting                                          */
            } CTSUAJTHR_b;
        };

        struct
        {
            __IOM uint16_t CTSUAJTHRL; /*!< (@ 0x0000005C) CTSU Automatic Judgment Control Register                   */
            __IOM uint16_t CTSUAJTHRH; /*!< (@ 0x0000005E) CTSU Automatic Judgment Control Register                   */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJMMAR;       /*!< (@ 0x00000060) CTSU Threshold Register                                    */

            struct
            {
                __IOM uint32_t AJMMATI : 4;  /*!< [3..0] Moving Average Count                                               */
                uint32_t               : 1;
                __IOM uint32_t AJMMR   : 27; /*!< [31..5] Moving Average Result                                             */
            } CTSUAJMMAR_b;
        };

        struct
        {
            __IOM uint16_t CTSUAJMMARL; /*!< (@ 0x00000060) CTSU Threshold Register                                    */
            __IOM uint16_t CTSUAJMMARH; /*!< (@ 0x00000062) CTSU Threshold Register                                    */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJBLACT;      /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register         */

            struct
            {
                __IOM uint32_t AJBLACT : 32; /*!< [31..0] Automatic determination baseline average calculation
                                              *   bits                                                                      */
            } CTSUAJBLACT_b;
        };

        struct
        {
            __IOM uint16_t CTSUAJBLACTL; /*!< (@ 0x00000064) CTSU Baseline Average Intermediate Result Register         */
            __IOM uint16_t CTSUAJBLACTH; /*!< (@ 0x00000066) CTSU Baseline Average Intermediate Result Register         */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJBLAR;      /*!< (@ 0x00000068) CTSU Baseline Average Result Register                      */

            struct
            {
                __IOM uint32_t AJBLAC : 16; /*!< [15..0] Baseline Average Count                                            */
                __IOM uint32_t AJBLAR : 16; /*!< [31..16] Baseline Average Result                                          */
            } CTSUAJBLAR_b;
        };

        struct
        {
            __IOM uint16_t CTSUAJBLARL; /*!< (@ 0x00000068) CTSU Baseline Average Result Register                      */
            __IOM uint16_t CTSUAJBLARH; /*!< (@ 0x0000006A) CTSU Baseline Average Result Register                      */
        };
    };

    union
    {
        union
        {
            __IOM uint32_t CTSUAJRR;      /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */

            struct
            {
                __IOM uint32_t TJR0 : 1;  /*!< [0..0] The judgment result when using SUCLK0 is stored.                   */
                __IOM uint32_t TJR1 : 1;  /*!< [1..1] The judgment result when using SUCLK1 is stored.                   */
                __IOM uint32_t TJR2 : 1;  /*!< [2..2] The judgment result when using SUCLK2 is stored.                   */
                __IOM uint32_t TJR3 : 1;  /*!< [3..3] The judgment result when using SUCLK3 is stored.                   */
                __IOM uint32_t FJR  : 1;  /*!< [4..4] The final judgment result on multi-clock measurement
                                           *   is stored.                                                                */
                uint32_t             : 3;
                __IOM uint32_t SJCCR : 8; /*!< [15..8] Remaining Number of Consecutive Detections                        */
                uint32_t             : 16;
            } CTSUAJRR_b;
        };
        __IOM uint16_t CTSUAJRRL;         /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */

        struct
        {
            __IOM uint8_t CTSUAJRR0;      /*!< (@ 0x0000006C) CTSU Automatic Judgment Result Register                    */
            __IOM uint8_t CTSUAJRR1;      /*!< (@ 0x0000006D) CTSU Automatic Judgment Result Register                    */
        };
    };
} R_CTSU2_Type;                           /*!< Size = 112 (0x70)                                                         */

/* =========================================================================================================================== */
/* ================                                           R_DAC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief D/A Converter (R_DAC)
 */

typedef struct                         /*!< (@ 0x40171000) R_DAC Structure                                            */
{
    union
    {
        __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */

        struct
        {
            __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
                                        *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
                                        *   = 1, the low-order 4 bits are fixed to 0: left justified
                                        *   format.                                                                   */
        } DADR_b[2];
    };

    union
    {
        __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */

        struct
        {
            uint8_t             : 5;
            __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
            __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
            __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
        } DACR_b;
    };

    union
    {
        __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */

        struct
        {
            uint8_t             : 7;
            __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
        } DADPR_b;
    };

    union
    {
        __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */

        struct
        {
            uint8_t              : 7;
            __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
        } DAADSCR_b;
    };

    union
    {
        __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */

        struct
        {
            __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
            uint8_t           : 5;
        } DAVREFCR_b;
    };

    union
    {
        __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */

        struct
        {
            uint8_t              : 6;
            __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
            __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
        } DAAMPCR_b;
    };

    union
    {
        __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */

        struct
        {
            __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
            uint8_t              : 7;
        } DAPC_b;
    };
    __IM uint16_t RESERVED[9];

    union
    {
        __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */

        struct
        {
            uint8_t              : 6;
            __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
                                        *   to wait for stabilization of the output amplifier of D/A
                                        *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
                                        *   but the conversion result D/A is not output from channel
                                        *   0. When the DAASW0 bit is 0, the stabilization wait time
                                        *   stops, and the D/A conversion result of channel 0 is output
                                        *   through the output amplifier.                                             */
            __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
                                        *   to wait for stabilization of the output amplifier of D/A
                                        *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
                                        *   but the conversion result D/A is not output from channel
                                        *   1. When the DAASW1 bit is 0, the stabilization wait time
                                        *   stops, and the D/A conversion result of channel 1 is output
                                        *   through the output amplifier.                                             */
        } DAASWCR_b;
    };
    __IM uint8_t  RESERVED1;
    __IM uint16_t RESERVED2[2129];

    union
    {
        __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */

        struct
        {
            __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
                                         *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
                                         *   select unit 0 as the target synchronous unit for the MCU.
                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
                                         *   conversions, select the target unit in this register in
                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
                                         *   is set to 0.                                                              */
            __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
                                         *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
                                         *   select unit 1 as the target synchronous unit for the MCU.
                                         *   When setting the DAADSCR.DAADST bit to 1 for synchronous
                                         *   conversions, select the target unit in this register in
                                         *   advance. Only set the DAADUSR register while the ADCSR.ADST
                                         *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
                                         *   is set to 0.                                                              */
            uint8_t : 6;
        } DAADUSR_b;
    };
    __IM uint8_t  RESERVED3;
    __IM uint16_t RESERVED4;
} R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */

/* =========================================================================================================================== */
/* ================                                          R_DEBUG                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Debug Function (R_DEBUG)
 */

typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
{
    union
    {
        __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */

        struct
        {
            uint32_t                   : 28;
            __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
            __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
            uint32_t                   : 2;
        } DBGSTR_b;
    };
    __IM uint32_t RESERVED[3];

    union
    {
        __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */

        struct
        {
            __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
            __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
            uint32_t                     : 12;
            __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
            __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
            __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
            __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
            __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
            uint32_t                     : 5;
            __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
            __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
            uint32_t                     : 5;
            __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
        } DBGSTOPCR_b;
    };
    __IM uint32_t RESERVED1[123];

    union
    {
        __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */

        struct
        {
            __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
            __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
            uint32_t              : 6;
            __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
            uint32_t              : 21;
        } FSBLSTAT_b;
    };
} R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */

/* =========================================================================================================================== */
/* ================                                           R_DMA                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief DMA Controller Common (R_DMA)
 */

typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
{
    union
    {
        __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */

        struct
        {
            __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
            uint8_t            : 7;
        } DMAST_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2[3];

    union
    {
        __IOM uint8_t DMCTL;           /*!< (@ 0x00000010) DMAC Control Register                                      */

        struct
        {
            __IOM uint8_t PR   : 1;    /*!< [0..0] Priority Control Select                                            */
            uint8_t            : 3;
            __IOM uint8_t ERCH : 1;    /*!< [4..4] Clear Channel Select                                               */
            uint8_t            : 3;
        } DMCTL_b;
    };
    __IM uint8_t  RESERVED3;
    __IM uint16_t RESERVED4;
    __IM uint32_t RESERVED5[11];

    union
    {
        __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */

        struct
        {
            __IM uint32_t DMECH    : 4; /*!< [3..0] DMAC Error channel                                                 */
            uint32_t               : 4;
            __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
            uint32_t               : 7;
            __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
            uint32_t               : 15;
        } DMECHR_b;
    };
    __IM uint32_t RESERVED6[15];

    union
    {
        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */

        struct
        {
            __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
            uint32_t            : 7;
            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
                                        *   IR flag is prohibited.                                                    */
            uint32_t : 15;
        } DELSR_b[8];
    };
} R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */

/* =========================================================================================================================== */
/* ================                                          R_DMAC0                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief DMA Controller (R_DMAC0)
 */

typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
{
    union
    {
        __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */

        struct
        {
            __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
        } DMSAR_b;
    };

    union
    {
        __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */

        struct
        {
            __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
        } DMDAR_b;
    };

    union
    {
        __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */

        struct
        {
            __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
            __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
            uint32_t              : 6;
        } DMCRA_b;
    };

    union
    {
        __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */

        struct
        {
            __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
                                         *   transfer counter.                                                         */
            __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
                                         *   repeat transfer operations.                                               */
        } DMCRB_b;
    };

    union
    {
        __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */

        struct
        {
            __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
            uint16_t            : 6;
            __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
            __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
            uint16_t            : 1;
            __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
            __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
        } DMTMD_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */

        struct
        {
            __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
                                        *   Enable                                                                    */
            __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
                                        *   Enable                                                                    */
            __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
            __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
            __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
            uint8_t             : 3;
        } DMINT_b;
    };

    union
    {
        __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */

        struct
        {
            __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
                                        *   extended repeat area on the destination address. For details
                                        *   on the settings.                                                          */
            __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
            __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
            __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
                                        *   repeat area on the source address. For details on the settings.           */
            __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
            __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
        } DMAMD_b;
    };
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */

        struct
        {
            __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
                                        *   as the address update mode for transfer source or destination.            */
        } DMOFR_b;
    };

    union
    {
        __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */

        struct
        {
            __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
            uint8_t           : 7;
        } DMCNT_b;
    };

    union
    {
        __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */

        struct
        {
            __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
            uint8_t             : 3;
            __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
            uint8_t             : 3;
        } DMREQ_b;
    };

    union
    {
        __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */

        struct
        {
            __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
            uint8_t            : 3;
            __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
            uint8_t            : 2;
            __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
        } DMSTS_b;
    };
    __IM uint8_t   RESERVED2;
    __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
    __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */

    union
    {
        __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */

        struct
        {
            __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
                                         *   mode                                                                      */
            __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
                                         *   mode                                                                      */
        } DMSBS_b;
    };

    union
    {
        __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */

        struct
        {
            __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
                                         *   mode                                                                      */
            __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
                                         *   mode                                                                      */
        } DMDBS_b;
    };

    union
    {
        __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */

        struct
        {
            __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
            uint8_t           : 7;
        } DMBWR_b;
    };
    __IM uint8_t  RESERVED3;
    __IM uint16_t RESERVED4;
} R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */

/* =========================================================================================================================== */
/* ================                                           R_DTC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Data Transfer Controller (R_DTC)
 */

typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
{
    union
    {
        __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */

        struct
        {
            uint8_t           : 4;
            __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
            uint8_t           : 3;
        } DTCCR_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */

        struct
        {
            __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.                                          */
        } DTCVBR_b;
    };

    union
    {
        __IOM uint8_t DTCADMOD;        /*!< (@ 0x00000008) DTC Address Mode Register                                  */

        struct
        {
            __IOM uint8_t SHORT : 1;   /*!< [0..0] Short-Address Mode Set                                             */
            uint8_t             : 7;
        } DTCADMOD_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */

        struct
        {
            __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
            uint8_t             : 7;
        } DTCST_b;
    };
    __IM uint8_t RESERVED4;

    union
    {
        __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */

        struct
        {
            __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
                                        *   the vector number for the activating source when DTC transfer
                                        *   is in progress.The value is only valid if DTC transfer
                                        *   is in progress (the value of the ACT flag is 1)                           */
            uint16_t          : 7;
            __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
        } DTCSTS_b;
    };

    union
    {
        __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */

        struct
        {
            uint8_t           : 4;
            __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
            uint8_t           : 3;
        } DTCCR_SEC_b;
    };
    __IM uint8_t  RESERVED5;
    __IM uint16_t RESERVED6;

    union
    {
        __IOM uint32_t DTCVBR_SEC;      /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */

        struct
        {
            __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.                                          */
        } DTCVBR_SEC_b;
    };

    union
    {
        __IOM uint32_t DTCDISP;          /*!< (@ 0x00000018) DTC Address Displacement Register                          */

        struct
        {
            __IOM uint32_t DTCDISP : 32; /*!< [31..0] DTC Address Displacement                                          */
        } DTCDISP_b;
    };
    __IM uint32_t RESERVED7;

    union
    {
        __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */

        struct
        {
            __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
            __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
            uint32_t              : 7;
            __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
            uint32_t              : 15;
        } DTEVR_b;
    };

    union
    {
        __IOM uint32_t DTCIBR;         /*!< (@ 0x00000024) DTC Index Table Base Register                              */

        struct
        {
            uint32_t              : 10;
            __IOM uint32_t DTCIBR : 22; /*!< [31..10] DTC Index Table Base Address                                     */
        } DTCIBR_b;
    };

    union
    {
        __IOM uint8_t DTCOR;           /*!< (@ 0x00000028) DTC Operation Register                                     */

        struct
        {
            __IOM uint8_t SQTFRL : 1;  /*!< [0..0] Sequence Transfer Stop                                             */
            uint8_t              : 7;
        } DTCOR_b;
    };
    __IM uint8_t  RESERVED8;
    __IM uint16_t RESERVED9;

    union
    {
        __IOM uint16_t DTCSQE;         /*!< (@ 0x0000002C) DTC Sequence Transfer Enable Register                      */

        struct
        {
            __IOM uint16_t VECN   : 8; /*!< [7..0] DTC Sequence Transfer Vector Number Specified                      */
            uint16_t              : 7;
            __IOM uint16_t ESPSEL : 1; /*!< [15..15] DTC Sequence Transfer Enable                                     */
        } DTCSQE_b;
    };
    __IM uint16_t RESERVED10;
} R_DTC_Type;                          /*!< Size = 48 (0x30)                                                          */

/* =========================================================================================================================== */
/* ================                                           R_ELC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Event Link Controller (R_ELC)
 */

typedef struct                         /*!< (@ 0x40082000) R_ELC Structure                                            */
{
    union
    {
        __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */

        struct
        {
            uint8_t             : 7;
            __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
        } ELCR_b;
    };
    __IM uint8_t            RESERVED;
    __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
    __IM uint16_t           RESERVED1[5];
    __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
    __IM uint16_t           RESERVED2[4];

    union
    {
        __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
                                         *                  A                                                          */

        struct
        {
            __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
            __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
                                         *   Attribution                                                               */
            __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
                                         *   Attribution                                                               */
            uint16_t : 13;
        } ELCSARA_b;
    };
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
                                        *                  B                                                          */

        struct
        {
            __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
            __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
            __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
            __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
            __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
            __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
            __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
            __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
            __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
            __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
            __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
            __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
            __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
            __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
            __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
            __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
        } ELCSARB_b;
    };
    __IM uint16_t RESERVED4;

    union
    {
        __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
                                        *                  C                                                          */

        struct
        {
            __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
            __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
            __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
            uint16_t              : 13;
        } ELCSARC_b;
    };
} R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */

/* =========================================================================================================================== */
/* ================                                       R_FACI_HP_CMD                                       ================ */
/* =========================================================================================================================== */

/**
 * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
 */

typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
{
    union
    {
        __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
        __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
    };
} R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */

/* =========================================================================================================================== */
/* ================                                         R_FACI_HP                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief Flash Application Command Interface (R_FACI_HP)
 */

typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
{
    __IM uint32_t RESERVED[4];

    union
    {
        __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */

        struct
        {
            uint8_t             : 3;
            __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
            __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
            uint8_t             : 2;
            __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
        } FASTAT_b;
    };
    __IM uint8_t  RESERVED1;
    __IM uint16_t RESERVED2;

    union
    {
        __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */

        struct
        {
            uint8_t               : 3;
            __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
            __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
            uint8_t               : 2;
            __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
        } FAEINT_b;
    };
    __IM uint8_t  RESERVED3;
    __IM uint16_t RESERVED4;

    union
    {
        __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */

        struct
        {
            __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
            uint8_t              : 7;
        } FRDYIE_b;
    };
    __IM uint8_t  RESERVED5;
    __IM uint16_t RESERVED6;
    __IM uint32_t RESERVED7[5];

    union
    {
        __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */

        struct
        {
            __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
                                        *   These bits can be written when FRDY bit of FSTATR register
                                        *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
        } FSADDR_b;
    };

    union
    {
        __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */

        struct
        {
            __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
                                        *   end address of target area in 'Blank Check' command. These
                                        *   bits can be written when FRDY bit of FSTATR register is
                                        *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
        } FEADDR_b;
    };
    __IM uint32_t RESERVED8[3];

    union
    {
        __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */

        struct
        {
            __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
                                        *   is only possible when the FRDY bit in the FSTATR register
                                        *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
                                        *   to this bit is only possible when 16 bits are written and
                                        *   the value written to the KEY bits is D9h.Written values
                                        *   are not retained by these bits (always read as 0x00).Only
                                        *   secure access can write to this register. Both secure access
                                        *   and non-secure read access are allowed. Non-secure writeaccess
                                        *   is denied, but TrustZo                                                    */
            uint16_t          : 7;
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FMEPROT_b;
    };
    __IM uint16_t RESERVED9;

    union
    {
        __IOM uint8_t FCNTSELR;        /*!< (@ 0x00000048) Flash Counter Select Register                              */

        struct
        {
            __IOM uint8_t CNTSEL : 3;  /*!< [2..0] Counter Select                                                     */
            uint8_t              : 5;
        } FCNTSELR_b;
    };
    __IM uint8_t  RESERVED10;
    __IM uint16_t RESERVED11;

    union
    {
        __IM uint32_t FCNTDATAR0;       /*!< (@ 0x0000004C) Flash Counter Data Register 0                              */

        struct
        {
            __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data                                                 */
        } FCNTDATAR0_b;
    };

    union
    {
        __IM uint32_t FCNTDATAR1;       /*!< (@ 0x00000050) Flash Counter Data Register 1                              */

        struct
        {
            __IM uint32_t CNTRDAT : 32; /*!< [31..0] Counter Read Data                                                 */
        } FCNTDATAR1_b;
    };
    __IM uint32_t RESERVED12[9];

    union
    {
        __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */

        struct
        {
            __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
                                        *   written when the FRDY bit in the FSTATR register is 1.
                                        *   Writing to this bit is ignored when the FRDY bit is 0.Writing
                                        *   to this bit is only possible when 16 bits are written and
                                        *   the value written to the KEY[7:0] bits is 0x78.Written
                                        *   values are not retained by these bits (always read as 0x00).              */
            uint16_t          : 7;
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FBPROT0_b;
    };
    __IM uint16_t RESERVED13;

    union
    {
        __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */

        struct
        {
            __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
                                        *   is only possible when the FRDY bit in the FSTATR register
                                        *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
                                        *   to this bit is only possible when 16 bits are written and
                                        *   the value written to the KEY[7:0] bits is 0xB1.Written
                                        *   values are not retained by these bits (always read as 0x00).              */
            uint16_t          : 7;
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FBPROT1_b;
    };
    __IM uint16_t RESERVED14;

    union
    {
        __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */

        struct
        {
            uint32_t                 : 6;
            __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
            uint32_t                 : 1;
            __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
            __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
            __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
            __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
            __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
            __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
            __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
            __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
            uint32_t                 : 4;
            __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
            __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
            __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
            __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
            uint32_t                 : 8;
        } FSTATR_b;
    };

    union
    {
        __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */

        struct
        {
            __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
                                         *   only when this register is accessed in 16-bit size and
                                         *   H'AA is written to KEY bits                                               */
            uint16_t               : 6;
            __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
                                         *   FRDY bit in FSTATR register is '1'. Writing to this bit
                                         *   in FRDY = '0' is ignored. Writing to these bits is enabled
                                         *   only when this register is accessed in 16-bit size and
                                         *   H'AA is written to KEY bits.                                              */
            __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
        } FENTRYR_b;
    };
    __IM uint16_t RESERVED15;
    __IM uint32_t RESERVED16;

    union
    {
        __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */

        struct
        {
            __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
                                        *   bit of FSTATR register is '1'. Writing to this bit in FRDY
                                        *   = '0' is ignored. Writing to these bits is enabled only
                                        *   when this register is accessed in 16-bit size and H'2D
                                        *   is written to KEY bits.                                                   */
            uint16_t          : 7;
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FSUINITR_b;
    };
    __IM uint16_t RESERVED17;
    __IM uint32_t RESERVED18[4];

    union
    {
        __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */

        struct
        {
            __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
            __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
        } FCMDR_b;
    };
    __IM uint16_t RESERVED19;
    __IM uint32_t RESERVED20[11];

    union
    {
        __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */

        struct
        {
            __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
            uint8_t             : 7;
        } FBCCNT_b;
    };
    __IM uint8_t  RESERVED21;
    __IM uint16_t RESERVED22;

    union
    {
        __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */

        struct
        {
            __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
            uint8_t           : 7;
        } FBCSTAT_b;
    };
    __IM uint8_t  RESERVED23;
    __IM uint16_t RESERVED24;

    union
    {
        union
        {
            __IM uint32_t FPSADDR;        /*!< (@ 0x000000D8) Programmed Area Start Address                              */

            struct
            {
                __IM uint32_t PSADR : 19; /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
                                           *   of the first programmed data which is found in 'Blank Check'
                                           *   command execution.                                                        */
                uint32_t : 13;
            } FPSADDR_b;
        };

        union
        {
            __IOM uint32_t FBCADDR;       /*!< (@ 0x000000D8) Flash Blank Check Address Register                         */

            struct
            {
                __IM uint32_t BCADR : 24; /*!< [23..0] Blank Check Address NOTE: Indicates the first fail address
                                           *   or the last blank checked address which is found in 'Blank
                                           *   Check' command execution.                                                 */
                uint32_t : 8;
            } FBCADDR_b;
        };
    };

    union
    {
        __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */

        struct
        {
            __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
                                        *   indicate the start sector address for setting the access
                                        *   window that is located in the configuration area.                         */
            uint32_t           : 4;
            __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
                                        *   Flag and Temporary Boot Swap Control and 'Config Clear'
                                        *   command execution                                                         */
            __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
                                        *   indicate the end sector address for setting the access
                                        *   window that is located in the configuration area.                         */
            uint32_t            : 4;
            __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
        } FAWMON_b;
    };

    union
    {
        __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */

        struct
        {
            __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
            uint16_t               : 15;
        } FCPSR_b;
    };
    __IM uint16_t RESERVED25;

    union
    {
        __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */

        struct
        {
            __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
                                        *   can be written when FRDY bit in FSTATR register is '1'.
                                        *   Writing to this bit in FRDY = '0' is ignored. Writing to
                                        *   these bits is enabled only when this register is accessed
                                        *   in 16-bit size and H'1E is written to KEY bits.                           */
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FPCKAR_b;
    };
    __IM uint16_t RESERVED26;

    union
    {
        __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */

        struct
        {
            __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
                                        *   bit in FSTATR register is '1'. Writing to this bit in FRDY
                                        *   = '0' is ignored. Writing to these bits is enabled only
                                        *   when this register is accessed in 16-bit size and H'66
                                        *   is written to KEY bits.                                                   */
            uint16_t          : 6;
            __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
        } FSUACR_b;
    };
    __IM uint16_t RESERVED27;
} R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */

/* =========================================================================================================================== */
/* ================                                         R_FACI_LP                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief Flash Application Command Interface (R_FACI_LP)
 */

typedef struct                         /*!< (@ 0x407EC000) R_FACI_LP Structure                                        */
{
    __IM uint32_t RESERVED[36];
    __IOM uint8_t DFLCTL;              /*!< (@ 0x00000090) Flash P/E Mode Control Register                            */
    __IM uint8_t  RESERVED1;
    __IM uint16_t RESERVED2;
    __IM uint32_t RESERVED3[27];

    union
    {
        __IOM uint8_t FPMCR;           /*!< (@ 0x00000100) Flash P/E Mode Control Register                            */

        struct
        {
            uint8_t            : 1;
            __IOM uint8_t FMS0 : 1;    /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
                                        *   011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
                                        *   P/E mode 010: Data flash P/E mode Others: Setting prohibited.             */
            uint8_t             : 1;
            __IOM uint8_t RPDIS : 1;   /*!< [3..3] Code Flash P/E Disable                                             */
            __IOM uint8_t FMS1  : 1;   /*!< [4..4] The bit to make data flash a programming modeRefer to
                                        *   the description of the FMS0 bit.                                          */
            uint8_t            : 1;
            __IOM uint8_t VLPE : 1;    /*!< [6..6] Low-Voltage P/E Mode Enable                                        */
            __IOM uint8_t FMS2 : 1;    /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
                                        *   of the FMS0 bit.                                                          */
        } FPMCR_b;
    };
    __IM uint8_t  RESERVED4;
    __IM uint16_t RESERVED5;

    union
    {
        __IOM uint8_t FASR;            /*!< (@ 0x00000104) Flash Area Select Register                                 */

        struct
        {
            __IOM uint8_t EXS : 1;     /*!< [0..0] Extra area select                                                  */
            uint8_t           : 7;
        } FASR_b;
    };
    __IM uint8_t  RESERVED6;
    __IM uint16_t RESERVED7;

    union
    {
        __IOM uint16_t FSARL;             /*!< (@ 0x00000108) Flash Processing Start Address Register L                  */

        struct
        {
            __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address                                                     */
        } FSARL_b;
    };
    __IM uint16_t RESERVED8;
    __IM uint32_t RESERVED9;

    union
    {
        __IOM uint16_t FSARH;             /*!< (@ 0x00000110) Flash Processing Start Address Register H                  */

        struct
        {
            __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address                                                      */
            uint16_t                 : 4;
            __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address                                                     */
        } FSARH_b;
    };
    __IM uint16_t RESERVED10;

    union
    {
        __IOM uint8_t FCR;             /*!< (@ 0x00000114) Flash Control Register                                     */

        struct
        {
            __IOM uint8_t CMD  : 4;    /*!< [3..0] Software Command Setting                                           */
            __IOM uint8_t DRC  : 1;    /*!< [4..4] Data Read Completion                                               */
            uint8_t            : 1;
            __IOM uint8_t STOP : 1;    /*!< [6..6] Forced Processing Stop                                             */
            __IOM uint8_t OPST : 1;    /*!< [7..7] Processing Start                                                   */
        } FCR_b;
    };
    __IM uint8_t  RESERVED11;
    __IM uint16_t RESERVED12;

    union
    {
        __IOM uint16_t FEARL;             /*!< (@ 0x00000118) Flash Processing End Address Register L                    */

        struct
        {
            __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address                                                       */
        } FEARL_b;
    };
    __IM uint16_t RESERVED13;
    __IM uint32_t RESERVED14;

    union
    {
        __IOM uint32_t FEARH;             /*!< (@ 0x00000120) Flash Processing End Address Register H                    */

        struct
        {
            __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address                                                        */
            uint32_t                 : 4;
            __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address                                                       */
            uint32_t                 : 16;
        } FEARH_b;
    };

    union
    {
        __IOM uint32_t FRESETR;        /*!< (@ 0x00000124) Flash Reset Register                                       */

        struct
        {
            __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers                                    */
            uint32_t              : 31;
        } FRESETR_b;
    };

    union
    {
        __IM uint32_t FSTATR00;         /*!< (@ 0x00000128) Flash Status Register00                                    */

        struct
        {
            __IM uint32_t ERERR0   : 1; /*!< [0..0] Erase Error Flag0                                                  */
            __IM uint32_t PRGERR0  : 1; /*!< [1..1] Program Error Flag0                                                */
            __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
            __IM uint32_t BCERR0   : 1; /*!< [3..3] Blank Check Error Flag0                                            */
            __IM uint32_t ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
            __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
            uint32_t               : 26;
        } FSTATR00_b;
    };

    union
    {
        __IM uint32_t FSTATR1;         /*!< (@ 0x0000012C) Flash Status Register1                                     */

        struct
        {
            uint32_t            : 1;
            __IM uint32_t DRRDY : 1;   /*!< [1..1] Data read request                                                  */
            uint32_t            : 4;
            __IM uint32_t FRDY  : 1;   /*!< [6..6] End status signal of a sequencer                                   */
            __IM uint32_t EXRDY : 1;   /*!< [7..7] End status signal of a Extra programming sequencer                 */
            uint32_t            : 24;
        } FSTATR1_b;
    };

    union
    {
        __IOM uint32_t FWBL0;          /*!< (@ 0x00000130) Flash Write Buffer Register L0                             */

        struct
        {
            __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
            uint32_t             : 16;
        } FWBL0_b;
    };
    __IM uint32_t RESERVED15;

    union
    {
        __IOM uint32_t FWBH0;          /*!< (@ 0x00000138) Flash Write Buffer Register H0                             */

        struct
        {
            __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
            uint32_t             : 16;
        } FWBH0_b;
    };

    union
    {
        __IM uint32_t FSTATR01;        /*!< (@ 0x0000013C) Flash Status Register01                                    */

        struct
        {
            __IM uint32_t ERERR1  : 1; /*!< [0..0] Erase Error Flag1                                                  */
            __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1                                                */
            uint32_t              : 1;
            __IM uint32_t BCERR1  : 1; /*!< [3..3] Blank Check Error Flag1                                            */
            uint32_t              : 28;
        } FSTATR01_b;
    };

    union
    {
        __IOM uint32_t FWBL1;               /*!< (@ 0x00000140) Flash Write Buffer Register L1                             */

        struct
        {
            __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command                               */
            uint32_t                  : 16;
        } FWBL1_b;
    };

    union
    {
        __IOM uint32_t FWBH1;               /*!< (@ 0x00000144) Flash Write Buffer Register H1                             */

        struct
        {
            __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command                               */
            uint32_t                  : 16;
        } FWBH1_b;
    };

    union
    {
        __IM uint32_t FRBL1;               /*!< (@ 0x00000148) Flash Read Buffer Register L1                              */

        struct
        {
            __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command                         */
            uint32_t                 : 16;
        } FRBL1_b;
    };

    union
    {
        __IM uint32_t FRBH1;               /*!< (@ 0x0000014C) Flash Read Buffer Register H1                              */

        struct
        {
            __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command                         */
            uint32_t                 : 16;
        } FRBH1_b;
    };
    __IM uint32_t RESERVED16[12];

    union
    {
        __OM uint32_t FPR;             /*!< (@ 0x00000180) Protection Unlock Register                                 */

        struct
        {
            __OM uint32_t FPR : 8;     /*!< [7..0] Protection Unlock Register                                         */
            uint32_t          : 24;
        } FPR_b;
    };

    union
    {
        __IM uint32_t FPSR;            /*!< (@ 0x00000184) Protection Unlock Status Register                          */

        struct
        {
            __IM uint32_t PERR : 1;    /*!< [0..0] Protect Error Flag                                                 */
            uint32_t           : 31;
        } FPSR_b;
    };

    union
    {
        __IM uint32_t FRBL0;           /*!< (@ 0x00000188) Flash Read Buffer Register L0                              */

        struct
        {
            __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
            uint32_t            : 16;
        } FRBL0_b;
    };
    __IM uint32_t RESERVED17;

    union
    {
        __IM uint32_t FRBH0;           /*!< (@ 0x00000190) Flash Read Buffer Register H0                              */

        struct
        {
            __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
            uint32_t            : 16;
        } FRBH0_b;
    };
    __IM uint32_t RESERVED18[11];

    union
    {
        __IM uint32_t FSCMR;           /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register                    */

        struct
        {
            uint32_t            : 8;
            __IM uint32_t SASMF : 1;   /*!< [8..8] Start-up Area Setting Monitor Flag                                 */
            uint32_t            : 5;
            __IM uint32_t FSPR  : 1;   /*!< [14..14] Access Window Protection Flag                                    */
            uint32_t            : 17;
        } FSCMR_b;
    };
    __IM uint32_t RESERVED19;

    union
    {
        __IM uint32_t FAWSMR;          /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register         */

        struct
        {
            __IM uint32_t FAWS : 12;   /*!< [11..0] Flash Access Window Start Address                                 */
            uint32_t           : 20;
        } FAWSMR_b;
    };
    __IM uint32_t RESERVED20;

    union
    {
        __IM uint32_t FAWEMR;          /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register           */

        struct
        {
            __IM uint32_t FAWE : 12;   /*!< [11..0] Flash Access Window End Address                                   */
            uint32_t           : 20;
        } FAWEMR_b;
    };
    __IM uint32_t RESERVED21;

    union
    {
        __IOM uint32_t FISR;           /*!< (@ 0x000001D8) Flash Initial Setting Register                             */

        struct
        {
            __IOM uint32_t PCKA : 6;   /*!< [5..0] Peripheral Clock Notification                                      */
            __IOM uint32_t SAS  : 2;   /*!< [7..6] Temporary boot swap mode                                           */
            uint32_t            : 24;
        } FISR_b;
    };

    union
    {
        __IOM uint32_t FEXCR;          /*!< (@ 0x000001DC) Flash Extra Area Control Register                          */

        struct
        {
            __IOM uint32_t CMD  : 3;   /*!< [2..0] Processing Start)                                                  */
            uint32_t            : 4;
            __IOM uint32_t OPST : 1;   /*!< [7..7] Software Command Setting                                           */
            uint32_t            : 24;
        } FEXCR_b;
    };

    union
    {
        __IM uint32_t FEAML;           /*!< (@ 0x000001E0) Flash Error Address Monitor Register L                     */

        struct
        {
            __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
            uint32_t           : 16;
        } FEAML_b;
    };
    __IM uint32_t RESERVED22;

    union
    {
        __IM uint32_t FEAMH;           /*!< (@ 0x000001E8) Flash Error Address Monitor Register H                     */

        struct
        {
            __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
            uint32_t           : 16;
        } FEAMH_b;
    };
    __IM uint32_t RESERVED23;

    union
    {
        __IM uint32_t FSTATR2;           /*!< (@ 0x000001F0) Flash Status Register2                                     */

        struct
        {
            __IM uint32_t  ERERR    : 1; /*!< [0..0] Erase Error Flag                                                   */
            __IM uint32_t  PRGERR1  : 1; /*!< [1..1] Program Error Flag                                                 */
            __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
            __IM uint32_t  BCERR    : 1; /*!< [3..3] Blank Check Error Flag                                             */
            __IM uint32_t  ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
            __IM uint32_t  EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
            uint32_t                : 26;
        } FSTATR2_b;
    };
    __IM uint32_t RESERVED24[3];

    union
    {
        __IOM uint8_t HIOTRM;          /*!< (@ 0x00000200) High-speed On-chip Oscillator Trimming Register            */

        struct
        {
            __IOM uint8_t HIOTRM : 6;  /*!< [5..0] HOCO User Trimming                                                 */
            uint8_t              : 2;
        } HIOTRM_b;
    };
    __IM uint8_t  RESERVED25;
    __IM uint16_t RESERVED26;
    __IM uint32_t RESERVED27;
    __IM uint16_t RESERVED28;

    union
    {
        __IOM uint8_t FLMODE;          /*!< (@ 0x0000020A) Flash Operating Mode Control Register                      */

        struct
        {
            uint8_t            : 6;
            __IOM uint8_t MODE : 2;    /*!< [7..6] Operating Mode Select                                              */
        } FLMODE_b;
    };

    union
    {
        __IOM uint8_t FLMWRP;          /*!< (@ 0x0000020B) Flash Operating Mode Protect Register                      */

        struct
        {
            __IOM uint8_t FLMWEN : 1;  /*!< [0..0] Control of Flash Operation Mode Select Register                    */
            uint8_t              : 7;
        } FLMWRP_b;
    };
    __IM uint32_t RESERVED29[89];

    union
    {
        __IOM uint32_t FCTLFR;          /*!< (@ 0x00000370) Flash Control Flag Register                                */

        struct
        {
            __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting                                                  */
            uint32_t               : 29;
        } FCTLFR_b;
    };
    __IM uint32_t  RESERVED30[3855];
    __IOM uint16_t FENTRYR_MF4;        /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4                      */
    __IOM uint16_t FENTRYR;            /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register                              */
    __IM uint32_t  RESERVED31[3];
    __IOM uint8_t  FLWAITR;            /*!< (@ 0x00003FC0) Flash Wait Cycle Register                                  */
    __IM uint8_t   RESERVED32;
    __IM uint16_t  RESERVED33;

    union
    {
        __IOM uint8_t FLDWAITR;         /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash          */

        struct
        {
            __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash                            */
            uint8_t                : 7;
        } FLDWAITR_b;
    };
    __IM uint8_t  RESERVED34;
    __IM uint16_t RESERVED35;
    __IOM uint8_t PFBER;               /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register                            */
    __IM uint8_t  RESERVED36;
    __IM uint16_t RESERVED37;
    __IM uint32_t RESERVED38;

    union
    {
        __IOM uint16_t FBKPGCR;        /*!< (@ 0x00003FD0) Flash Bank Program Control Register                        */

        struct
        {
            __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable                                    */
            uint16_t              : 7;
            __OM uint16_t FEKEY   : 8; /*!< [15..8] Key Code                                                          */
        } FBKPGCR_b;
    };
    __IM uint16_t RESERVED39;

    union
    {
        __IOM uint16_t FBKSWCR;          /*!< (@ 0x00003FD4) Flash Bank Swap Control Register                           */

        struct
        {
            __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable                                            */
            uint16_t                : 7;
            __OM uint16_t FEKEY     : 8; /*!< [15..8] Key Code                                                          */
        } FBKSWCR_b;
    };
    __IM uint16_t RESERVED40;
} R_FACI_LP_Type;                        /*!< Size = 16344 (0x3fd8)                                                     */

/* =========================================================================================================================== */
/* ================                                        R_CTSUTRIM                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief CTSU Trimming Registers (R_CTSUTRIM)
 */

typedef struct                         /*!< (@ 0x407EC000) R_CTSUTRIM Structure                                       */
{
    __IM uint32_t RESERVED[233];

    union
    {
        __IOM uint32_t CTSUTRIMA;         /*!< (@ 0x000003A4) CTSU Trimming Register A                                   */

        struct
        {
            __IOM uint32_t RTRIM     : 8; /*!< [7..0] CTSU Reference Resistance Adjustment                               */
            __IOM uint32_t DACTRIM   : 8; /*!< [15..8] Linearity Adjustment of Offset Current                            */
            __IOM uint32_t SUADJD    : 8; /*!< [23..16] CTSU SUCLK Frequency Adjustment                                  */
            __IOM uint32_t SUADJTRIM : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
                                           *   (120k)                                                                    */
        } CTSUTRIMA_b;
    };

    union
    {
        __IOM uint32_t CTSUTRIMB;        /*!< (@ 0x000003A8) CTSU Trimming Register B                                   */

        struct
        {
            __IOM uint32_t TRESULT0 : 8; /*!< [7..0] Coefficient of variation for the reference load resistance
                                          *   (7.5k)                                                                    */
            __IOM uint32_t TRESULT1 : 8; /*!< [15..8] Coefficient of variation for the reference load resistance
                                          *   (15k)                                                                     */
            __IOM uint32_t TRESULT2 : 8; /*!< [23..16] Coefficient of variation for the reference load resistance
                                          *   (30k)                                                                     */
            __IOM uint32_t TRESULT3 : 8; /*!< [31..24] Coefficient of variation for the reference load resistance
                                          *   (60k)                                                                     */
        } CTSUTRIMB_b;
    };
} R_CTSUTRIM_Type;                       /*!< Size = 940 (0x3ac)                                                        */

/* =========================================================================================================================== */
/* ================                                         R_FCACHE                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Flash Memory Cache (R_FCACHE)
 */

typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
{
    __IM uint16_t RESERVED[128];

    union
    {
        __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */

        struct
        {
            __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
            uint16_t                : 15;
        } FCACHEE_b;
    };
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */

        struct
        {
            __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
            uint16_t                : 15;
        } FCACHEIV_b;
    };
    __IM uint16_t RESERVED2[11];

    union
    {
        __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */

        struct
        {
            __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
            uint8_t            : 5;
        } FLWT_b;
    };
    __IM uint8_t  RESERVED3;
    __IM uint16_t RESERVED4[17];

    union
    {
        __IOM uint16_t FSAR;               /*!< (@ 0x00000140) Flash Security Attribution Register                        */

        struct
        {
            __IOM uint16_t FLWTSA     : 1; /*!< [0..0] FLWT Security Attribution                                          */
            __IOM uint16_t PFBERSA    : 1; /*!< [1..1] PFBERSA Security Attribution                                       */
            uint16_t                  : 6;
            __IOM uint16_t FCKMHZSA   : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
            __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI Command Issuing Security Attribution                          */
            __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI Command registera Security Attribution                      */
            uint16_t                  : 4;
            __IOM uint16_t DFLCTLSA   : 1; /*!< [15..15] DFLCTL Security Attribution                                      */
        } FSAR_b;
    };
} R_FCACHE_Type;                           /*!< Size = 322 (0x142)                                                        */

/* =========================================================================================================================== */
/* ================                                          R_GPT0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief General PWM Timer (R_GPT0)
 */

typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure                                           */
{
    union
    {
        __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */

        struct
        {
            __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
            __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
            __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
            __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
            __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
            uint32_t             : 3;
            __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
            uint32_t             : 16;
        } GTWP_b;
    };

    union
    {
        __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */

        struct
        {
            __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
            __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter stop. 1
                                         *   means counter running.                                                    */
        } GTSTR_b;
    };

    union
    {
        __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */

        struct
        {
            __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
            __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
                                         *   counter status (GTCR.CST bit). 0 means counter runnning.
                                         *   1 means counter stop.                                                     */
        } GTSTP_b;
    };

    union
    {
        __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */

        struct
        {
            __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
            __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
            __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
        } GTCLR_b;
    };

    union
    {
        __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */

        struct
        {
            __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
            __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
            __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
            __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
            __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
            __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
            __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
            __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
            __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   Counter Start Enable                                                      */
            __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
            __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
            uint32_t              : 7;
            __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
        } GTSSR_b;
    };

    union
    {
        __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */

        struct
        {
            __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
            __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
            __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
            __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
            __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
            __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
            __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
            __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
            __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   Counter Stop Enable                                                       */
            __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
            __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
            uint32_t              : 7;
            __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
        } GTPSR_b;
    };

    union
    {
        __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */

        struct
        {
            __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
            __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
            __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
            __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
            __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
            __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
            __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
            __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
            __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   Counter Clear Enable                                                      */
            __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
            __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
                                          *   Source Counter Clear Enable.                                              */
            __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
                                          *   Enable (This bit is only available in GPT324 to GPT329.
                                          *   In GPT320 to GPT323, this bit is read as 0. The write value
                                          *   should be 0.)                                                             */
            uint32_t            : 3;
            __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
        } GTCSR_b;
    };

    union
    {
        __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */

        struct
        {
            __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
            __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
            __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
            __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
            __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
            __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
            __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
            __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
            __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   Counter Count Up Enable                                                   */
            __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
            __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
            uint32_t              : 4;
        } GTUPSR_b;
    };

    union
    {
        __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */

        struct
        {
            __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
            __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
            __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
            __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
            __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
            __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
            __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
            __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
            __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   Counter Count Down Enable                                                 */
            __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
            __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
            uint32_t              : 4;
        } GTDNSR_b;
    };

    union
    {
        __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
                                          *                  Register A                                                 */

        struct
        {
            __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
            __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
            __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
            __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
            __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   GTCCRA Input Capture Enable                                               */
            __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
            __IOM uint32_t ASOC   : 1;   /*!< [24..24] Other channel Source GTCCRA Input Capture Enable                 */
            uint32_t              : 7;
        } GTICASR_b;
    };

    union
    {
        __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
                                          *                  Register B                                                 */

        struct
        {
            __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
            __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
            __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
            __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
            __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
                                          *   Enable                                                                    */
            __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
                                          *   GTCCRB Input Capture Enable                                               */
            __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
            __IOM uint32_t BSOC   : 1;   /*!< [24..24] Other channel Source GTCCRB Input Capture Enable                 */
            uint32_t              : 7;
        } GTICBSR_b;
    };

    union
    {
        __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */

        struct
        {
            __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
            uint32_t               : 3;
            __IOM uint32_t AINV    : 1; /*!< [4..4] GTIOCnA input/output pin polarity reversal control                 */
            __IOM uint32_t BINV    : 1; /*!< [5..5] GTIOCnB input/output pin polarity reversal control                 */
            uint32_t               : 2;
            __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
            __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
            __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
            __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
            uint32_t               : 2;
            __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
            __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
            uint32_t               : 3;
            __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
            __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
            uint32_t               : 3;
        } GTCR_b;
    };

    union
    {
        __IOM uint32_t GTUDDTYC;        /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
                                         *                  Register                                                   */

        struct
        {
            __IOM uint32_t UD     : 1;  /*!< [0..0] Count Direction Setting                                            */
            __IOM uint32_t UDF    : 1;  /*!< [1..1] Forcible Count Direction Setting                                   */
            uint32_t              : 14;
            __IOM uint32_t OADTY  : 2;  /*!< [17..16] GTIOCA Output Duty Setting                                       */
            __IOM uint32_t OADTYF : 1;  /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
            __IOM uint32_t OADTYR : 1;  /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
                                         *   percent Duty Setting                                                      */
            uint32_t              : 4;
            __IOM uint32_t OBDTY  : 2;  /*!< [25..24] GTIOCB Output Duty Setting                                       */
            __IOM uint32_t OBDTYF : 1;  /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
            __IOM uint32_t OBDTYR : 1;  /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
                                         *   percent Duty Setting                                                      */
            __IOM uint32_t OABDTYT : 1; /*!< [28..28] GTIOCnA,B pin output 0%/100% duty setting reflection
                                         *   timing setting                                                            */
            uint32_t : 3;
        } GTUDDTYC_b;
    };

    union
    {
        __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */

        struct
        {
            __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
            __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
                                        *   Clear Disable.(This bit is only available in GPT324 to
                                        *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
                                        *   write value should be 0.)                                                 */
            __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
            __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
            __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
            __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
            __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
                                        *   GPT323, this bit is read as 0. The write value should be
                                        *   0.)                                                                       */
            __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
            __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
            __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
            __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
            uint32_t              : 1;
            __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
            __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
            __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
            __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
            __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
                                        *   bit is only available in GPT324 to GPT329. In GPT320 to
                                        *   GPT323, this bit is read as 0. The write value should be
                                        *   0.)                                                                       */
            uint32_t             : 1;
            __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
            __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
        } GTIOR_b;
    };

    union
    {
        __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */

        struct
        {
            __IOM uint32_t GTINTA : 1;   /*!< [0..0] GTCCRA Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTB : 1;   /*!< [1..1] GTCCRB Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTC : 1;   /*!< [2..2] GTCCRC Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTD : 1;   /*!< [3..3] GTCCRD Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTE : 1;   /*!< [4..4] GTCCRE Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTF : 1;   /*!< [5..5] GTCCRF Register Compare Match/Input Capture Interrupt
                                          *   Enable                                                                    */
            __IOM uint32_t GTINTPR : 2;  /*!< [7..6] GTPR Register Compare Match Interrupt Enable                       */
            __IOM uint32_t SCFA    : 1;  /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
                                          *   Clear Enable                                                              */
            __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
                                          *   Clear Enable                                                              */
            __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
                                          *   Synchronous Clear Enable                                                  */
            __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
                                          *   Synchronous Clear Enable                                                  */
            __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
                                          *   Synchronous Clear Enable                                                  */
            __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
                                          *   Synchronous Clear Enable                                                  */
            __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
            __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
            __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
                                          *   Start Request Enable                                                      */
            __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
                                          *   Conversion Start Request Enable                                           */
            __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
                                          *   Start Request Enable                                                      */
            __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
                                          *   Conversion Start Request Enable                                           */
            uint32_t               : 4;
            __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
            uint32_t               : 2;
            __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
            __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
            __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
            __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
        } GTINTAD_b;
    };

    union
    {
        __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */

        struct
        {
            __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
            __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
            __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
            __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
            __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
            __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
            __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
            __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
            __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
                                         *   for counting the number of times a timer interrupt has
                                         *   been skipped.)                                                            */
            uint32_t               : 4;
            __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
            __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
                                         *   Request Interrupt Enable                                                  */
            __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
                                         *   Start Request Flag                                                        */
            __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
                                         *   Request Flag                                                              */
            __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
                                         *   Start Request Flag                                                        */
            uint32_t             : 4;
            __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
            uint32_t             : 3;
            __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
            __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
            __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
            __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
        } GTST_b;
    };

    union
    {
        __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */

        struct
        {
            __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
            __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
            __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
            __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
            uint32_t               : 4;
            __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
            uint32_t               : 1;
            __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
            uint32_t               : 5;
            __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
            __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
            __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
            __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
                                         *   is read as 0.                                                             */
            uint32_t             : 1;
            __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
                                         *   at an underflow (in down-counting) or overflow (in up-counting)
                                         *   is performed.                                                             */
            __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
            uint32_t             : 1;
            __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
                                         *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
                                         *   at an underflow (in down-counting) or overflow (in up-counting)
                                         *   is performed.                                                             */
            __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
            uint32_t             : 1;
        } GTBER_b;
    };

    union
    {
        __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
                                        *                  Start Request Skipping Setting Register                    */

        struct
        {
            __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
            __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
            __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
            __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
            __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
            __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
            __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
            __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
            uint32_t             : 1;
            __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
            uint32_t             : 1;
            __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
            uint32_t             : 17;
        } GTITC_b;
    };

    union
    {
        __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */

        struct
        {
            __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
        } GTCNT_b;
    };

    union
    {
        __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */

        struct
        {
            __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
        } GTCCR_b[6];
    };

    union
    {
        __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */

        struct
        {
            __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
        } GTPR_b;
    };

    union
    {
        __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */

        struct
        {
            __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
        } GTPBR_b;
    };

    union
    {
        __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
                                         *                  Register                                                   */

        struct
        {
            __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
        } GTPDBR_b;
    };

    union
    {
        __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */

        struct
        {
            __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
        } GTADTRA_b;
    };

    union
    {
        __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
                                           *                  A                                                          */

        struct
        {
            __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
        } GTADTBRA_b;
    };

    union
    {
        __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
                                            *                  Register A                                                 */

        struct
        {
            __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
                                            *   A                                                                         */
        } GTADTDBRA_b;
    };

    union
    {
        __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */

        struct
        {
            __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
        } GTADTRB_b;
    };

    union
    {
        __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
                                           *                  B                                                          */

        struct
        {
            __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
        } GTADTBRB_b;
    };

    union
    {
        __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
                                            *                  Register B                                                 */

        struct
        {
            __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
                                            *   B                                                                         */
        } GTADTDBRB_b;
    };

    union
    {
        __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */

        struct
        {
            __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
            uint32_t             : 3;
            __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
            __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
            uint32_t             : 2;
            __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
            uint32_t             : 23;
        } GTDTCR_b;
    };

    union
    {
        __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */

        struct
        {
            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
        } GTDVU_b;
    };

    union
    {
        __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */

        struct
        {
            __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
        } GTDVD_b;
    };

    union
    {
        __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */

        struct
        {
            __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
        } GTDBU_b;
    };

    union
    {
        __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */

        struct
        {
            __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
        } GTDBD_b;
    };

    union
    {
        __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
                                        *                  Status Register                                            */

        struct
        {
            __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
            uint32_t          : 30;
        } GTSOS_b;
    };

    union
    {
        __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
                                        *                  Temporary Release Register                                 */

        struct
        {
            __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
            uint32_t            : 31;
        } GTSOTR_b;
    };

    union
    {
        __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
                                         *                  Signal Monitoring Register                                 */

        struct
        {
            __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
            uint32_t               : 6;
            __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
                                         *   Enabling                                                                  */
            uint32_t               : 7;
            __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
            uint32_t               : 6;
            __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
                                         *   Enabling                                                                  */
            uint32_t : 7;
        } GTADSMR_b;
    };

    union
    {
        __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
                                           *                  Counter Control Register                                   */

        struct
        {
            __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
            uint32_t               : 2;
            __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
            uint32_t               : 4;
            __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
            __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
                                           *   select                                                                    */
            uint32_t                 : 2;
            __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
            __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
            __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
        } GTEITC_b;
    };

    union
    {
        __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
                                        *                  Setting Register 1                                         */

        struct
        {
            __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
                                        *   Extended Skipping Function Select                                         */
            uint32_t             : 1;
            __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
                                        *   Extended Skipping Function Select                                         */
            uint32_t             : 1;
            __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
                                        *   Function Select                                                           */
            uint32_t             : 1;
            __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
                                        *   Function Select                                                           */
            uint32_t             : 1;
            __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
                                        *   Function Select                                                           */
            uint32_t             : 1;
            __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
                                        *   Function Select                                                           */
            uint32_t             : 1;
            __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
            uint32_t             : 1;
            __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
            uint32_t             : 1;
        } GTEITLI1_b;
    };

    union
    {
        __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
                                        *                  Setting Register 2                                         */

        struct
        {
            __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
                                        *   Skipping Function Select                                                  */
            uint32_t              : 1;
            __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
                                        *   Skipping Function Select                                                  */
            uint32_t : 25;
        } GTEITLI2_b;
    };

    union
    {
        __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
                                         *                  Setting Register                                           */

        struct
        {
            __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
                                         *   Select                                                                    */
            uint32_t              : 1;
            __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
                                         *   Select                                                                    */
            uint32_t              : 1;
            __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
                                         *   Select                                                                    */
            uint32_t               : 5;
            __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
                                         *   Function Select                                                           */
            uint32_t               : 1;
            __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
                                         *   Function Select                                                           */
            uint32_t               : 1;
            __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
                                         *   Select                                                                    */
            uint32_t               : 1;
            __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
                                         *   Select                                                                    */
            uint32_t : 1;
        } GTEITLB_b;
    };

    union
    {
        __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
                                          *                  Function Setting Register                                  */

        struct
        {
            __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
            uint32_t                : 1;
            __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
            uint32_t                : 6;
            __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
            uint32_t                : 1;
            __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
            uint32_t                : 6;
        } GTICLF_b;
    };

    union
    {
        __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */

        struct
        {
            __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
            uint32_t            : 7;
            __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
            uint32_t            : 7;
            __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
            uint32_t            : 4;
        } GTPC_b;
    };

    union
    {
        __IOM uint32_t GTADCMSC;            /*!< (@ 0x000000C0) General PWM Timer A/D Conversion Start Request
                                             *                  Compare Match Skipping Control Register                    */

        struct
        {
            __IOM uint32_t ADCMSC1 : 2;     /*!< [1..0] A/D Conversion Start Request Compare Match Skipping Counter
                                             *   1 Count Source Select                                                     */
            uint32_t               : 2;
            __IOM uint32_t ADCMST1 : 4;     /*!< [7..4] A/D Conversion Start Request Compare Match Skipping 1
                                             *   Skipping Count Setting                                                    */
            __IOM uint32_t ADCMSCNT1IV : 4; /*!< [11..8] A/D Conversion Start Request Compare Match Skipping
                                             *   Counter 1 Initial Value                                                   */
            __IM uint32_t ADCMSCNT1 : 4;    /*!< [15..12] A/D Conversion Start Request Compare Match Skipping
                                             *   Counter 1                                                                 */
            __IOM uint32_t ADCMSC2 : 2;     /*!< [17..16] A/D Conversion Start Request Compare Match Skipping
                                             *   Counter 2 Count Source Select                                             */
            uint32_t               : 2;
            __IOM uint32_t ADCMST2 : 4;     /*!< [23..20] A/D Conversion Start Request Compare Match Skipping
                                             *   2 Skipping Count Setting                                                  */
            __IOM uint32_t ADCMSCNT2IV : 4; /*!< [27..24] A/D Conversion Start Request Compare Match Skipping
                                             *   Counter 2 Initial Value                                                   */
            __IM uint32_t ADCMSCNT2 : 4;    /*!< [31..28] A/D Conversion Start Request Compare Match Skipping
                                             *   Counter 2                                                                 */
        } GTADCMSC_b;
    };

    union
    {
        __IOM uint32_t GTADCMSS;        /*!< (@ 0x000000C4) General PWM Timer A/D Conversion Start Request
                                         *                  Compare Match Skipping Setting Register                    */

        struct
        {
            __IOM uint32_t ADCMSAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Compare
                                         *   Match Skipping Function Select                                            */
            uint32_t               : 1;
            __IOM uint32_t ADCMSBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Compare
                                         *   Match Skipping Function Select                                            */
            uint32_t               : 9;
            __IOM uint32_t ADCMBSA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer by A/D Conversion
                                         *   Start Request Compare Match Skipping Function Select                      */
            uint32_t               : 1;
            __IOM uint32_t ADCMBSB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer by A/D Conversion
                                         *   Start Request Compare Match Skipping Function Select                      */
            uint32_t : 9;
        } GTADCMSS_b;
    };
    __IM uint32_t RESERVED[2];

    union
    {
        __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
                                         *                  Control Channel Select Register                            */

        struct
        {
            __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
                                         *   Select                                                                    */
            uint32_t : 22;
        } GTSECSR_b;
    };

    union
    {
        __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
                                        *                  Control Register                                           */

        struct
        {
            __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
            __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
            __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
            __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
            uint32_t             : 4;
            __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
            __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
            __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
            __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
            uint32_t             : 4;
            __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
            __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
            uint32_t             : 6;
            __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
            __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
            uint32_t             : 6;
        } GTSECR_b;
    };
    __IM uint32_t RESERVED1[2];

    union
    {
        __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */

        struct
        {
            __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
            __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
                                        *   Disable                                                                   */
            uint32_t             : 2;
            __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
                                        *   Enable                                                                    */
            __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
                                        *   Enable                                                                    */
            uint32_t              : 1;
            __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
                                        *   Enable                                                                    */
            __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
                                        *   Enable                                                                    */
            uint32_t             : 1;
            __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
                                        *   Disable                                                                   */
            __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
                                        *   Transfer Disable                                                          */
            uint32_t             : 2;
            __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
            __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
            __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
            __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
            uint32_t             : 2;
        } GTBER2_b;
    };

    union
    {
        __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */

        struct
        {
            __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
            uint32_t              : 11;
            __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
            uint32_t              : 11;
        } GTOLBR_b;
    };
    __IM uint32_t RESERVED2;

    union
    {
        __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
                                        *                  Capture Control Register                                   */

        struct
        {
            __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
            __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
                                        *   to Other Channel GTCCRA Input Capture Source Enable                       */
            __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
                                        *   Channel GTCCRA Input Capture Source Enable                                */
            __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
                                        *   Channel GTCCRA Input Capture Source Enable                                */
            __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
                                        *   Channel GTCCRA Input Capture Source Enable                                */
            __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
                                        *   Channel GTCCRA Input Capture Source Enable                                */
            __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
                                        *   Source Enable                                                             */
            __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
                                        *   Source Enable                                                             */
            __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
                                        *   Capture Source Enable                                                     */
            uint32_t              : 5;
            __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
            __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
            __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
                                        *   to Other Channel GTCCRB Input Capture Source Enable                       */
            __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
            __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
            __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
                                        *   Other Channel GTCCRb Input Capture Source Enable                          */
            __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
                                        *   Other Channel GTCCRB Input Capture Source Enable                          */
            __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
                                        *   Source Enable                                                             */
            __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
                                        *   Capture Source Enable                                                     */
            __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
                                        *   Capture Source Enable                                                     */
            uint32_t              : 5;
            __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
        } GTICCR_b;
    };
} R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */

/* =========================================================================================================================== */
/* ================                                         R_GPT_OPS                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief Output Phase Switching for GPT (R_GPT_OPS)
 */

typedef struct                         /*!< (@ 0x40169A00) R_GPT_OPS Structure                                        */
{
    union
    {
        __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */

        struct
        {
            __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
                                        *   by the software settings.This bit setting is valid when
                                        *   the OPSCR.FB bit = 1.                                                     */
            __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
                                        *   by the software settings.This bit setting is valid when
                                        *   the OPSCR.FB bit = 1.                                                     */
            __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
                                        *   by the software settings.This bit setting is valid when
                                        *   the OPSCR.FB bit = 1.                                                     */
            uint32_t        : 1;
            __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
                                        *   e settings (UF/VF/WF)                                                     */
            __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
                                        *   e settings (UF/VF/WF)                                                     */
            __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
                                        *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
                                        *   e settings (UF/VF/WF)                                                     */
            uint32_t          : 1;
            __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
            uint32_t          : 7;
            __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
                                        *   input phase from the software settings and external input.                */
            __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
            __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
            __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
            __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
            __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
            uint32_t             : 2;
            __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
            __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
            uint32_t             : 2;
            __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
            __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
                                        *   sampling clock setting of the external input.                             */
        } OPSCR_b;
    };
} R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */

/* =========================================================================================================================== */
/* ================                                        R_GPT_POEG0                                        ================ */
/* =========================================================================================================================== */

/**
 * @brief Port Output Enable for GPT (R_GPT_POEG0)
 */

typedef struct                         /*!< (@ 0x4008A000) R_GPT_POEG0 Structure                                      */
{
    union
    {
        __IOM uint32_t POEGG;          /*!< (@ 0x00000000) POEG Group Setting Register                                */

        struct
        {
            __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
            __IOM uint32_t IOCF  : 1;  /*!< [1..1] Real Time Overcurrent Detection Flag                               */
            __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
            __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
            __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
                                        *   once after a reset.                                                       */
            __IOM uint32_t IOCE : 1;   /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t OSTPE : 1;  /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            uint32_t             : 1;
            __IOM uint32_t CDRE0 : 1;  /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t CDRE1 : 1;  /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t CDRE2 : 1;  /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t CDRE3 : 1;  /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t CDRE4 : 1;  /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            __IOM uint32_t CDRE5 : 1;  /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
                                        *   only once after a reset.                                                  */
            uint32_t            : 2;
            __IM uint32_t ST    : 1;   /*!< [16..16] GTETRG Input Status Flag                                         */
            uint32_t            : 11;
            __IOM uint32_t INV  : 1;   /*!< [28..28] GTETRG Input Reverse                                             */
            __IOM uint32_t NFEN : 1;   /*!< [29..29] Noise Filter Enable                                              */
            __IOM uint32_t NFCS : 2;   /*!< [31..30] Noise Filter Clock Select                                        */
        } POEGG_b;
    };
    __IM uint32_t RESERVED[15];

    union
    {
        __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
                                        *                  Register                                                   */

        struct
        {
            __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
            uint16_t             : 7;
            __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
        } GTONCWP_b;
    };
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
                                        *                  Register                                                   */

        struct
        {
            __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
            uint16_t           : 3;
            __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
            __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
            uint16_t           : 7;
        } GTONCCR_b;
    };
    __IM uint16_t RESERVED2;
} R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */

/* =========================================================================================================================== */
/* ================                                           R_ICU                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Interrupt Controller Unit (R_ICU)
 */

typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
{
    union
    {
        __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */

        struct
        {
            __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
            uint8_t               : 1;
            __IOM uint8_t LOCOSEL : 1; /*!< [3..3] IRQi Digital Filter Sampling LOCO Clock Select                     */
            __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
            uint8_t               : 1;
            __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
        } IRQCR_b[16];
    };
    __IM uint32_t RESERVED[60];

    union
    {
        __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */

        struct
        {
            __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
            uint8_t                : 3;
            __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
            uint8_t                : 1;
            __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
        } NMICR_b;
    };
    __IM uint8_t  RESERVED1;
    __IM uint16_t RESERVED2;
    __IM uint32_t RESERVED3[7];

    union
    {
        __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */

        struct
        {
            __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
            __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
            __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
            __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
            __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
            uint16_t               : 1;
            __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
            __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
            __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
            __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
            __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
            __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
            __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
            __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
            uint16_t               : 1;
            __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
        } NMIER_b;
    };
    __IM uint16_t RESERVED4;
    __IM uint32_t RESERVED5[3];

    union
    {
        __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */

        struct
        {
            __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
            __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
            __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
            __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
            __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
            uint16_t               : 1;
            __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
            __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
            __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
            __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
            __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
            __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
            __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
            __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
            uint16_t               : 1;
            __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
        } NMICLR_b;
    };
    __IM uint16_t RESERVED6;
    __IM uint32_t RESERVED7[3];

    union
    {
        __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */

        struct
        {
            __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
            __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
            __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
            __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
            __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
            uint16_t              : 1;
            __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
            __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
            __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
            __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
            __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
            __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
            __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
            __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
            uint16_t              : 1;
            __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
        } NMISR_b;
    };
    __IM uint16_t RESERVED8;
    __IM uint32_t RESERVED9[23];

    union
    {
        __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */

        struct
        {
            __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
            __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
            __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
            __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
            __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
            __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
            __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
            uint32_t                    : 1;
            __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
            __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
            __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
            __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
            __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
            __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
            __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
            __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
                                              *   enable                                                                    */
            __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
                                              *   enable                                                                    */
            __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
        } WUPEN_b;
    };

    union
    {
        __IOM uint32_t WUPEN1;         /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */

        struct
        {
            uint32_t                 : 7;
            __IOM uint32_t SOSCWUPEN : 1; /*!< [7..7] Sub Oscillation Stop Detection Interrupt Software Standby/Snooze
                                           *   Mode Returns Enable Bit                                                   */
            uint32_t                : 3;
            __IOM uint32_t I3CWUPEN : 1;  /*!< [11..11] I3C Wakeup Condition Detection Interrupt Software Standby/Snooze
                                           *   Mode Returns Enable Bit                                                   */
            uint32_t : 20;
        } WUPEN1_b;
    };

    union
    {
        __IOM uint32_t WUPEN2;                 /*!< (@ 0x000001A8) Wake Up Interrupt Enable Register 2                        */

        struct
        {
            __IOM uint32_t INTUR0WUPEN : 1;    /*!< [0..0] UARTA0_INTUR Interrupt Software Standby/Snooze Mode Return
                                                *   Enable                                                                    */
            __IOM uint32_t INTURE0WUPEN : 1;   /*!< [1..1] UARTA0_INTURE Interrupt Software Standby/Snooze Mode
                                                *   Return Enable                                                             */
            __IOM uint32_t INTUR1WUPEN : 1;    /*!< [2..2] UARTA1_INTUR Interrupt Software Standby/Snooze Mode Return
                                                *   Enable                                                                    */
            __IOM uint32_t INTURE1WUPEN : 1;   /*!< [3..3] UARTA1_INTURE Interrupt Software Standby/Snooze Mode
                                                *   Return Enable                                                             */
            __IOM uint32_t EXLVDVBATWUPEN : 1; /*!< [4..4] LVD_EXLVDVBAT Interrupt Software Standby/Snooze Mode
                                                *   Returns Enable Bit                                                        */
            __IOM uint32_t LVDVRTCWUPEN : 1;   /*!< [5..5] LVD_VRTC Interrupt Software Standby/Snooze Mode Returns
                                                *   Enable Bit                                                                */
            __IOM uint32_t EXLVDWUPEN : 1;     /*!< [6..6] LVD_EXLVD Interrupt Software Standby/Snooze Mode Returns
                                                *   Enable Bit                                                                */
            uint32_t : 25;
        } WUPEN2_b;
    };
    __IM uint32_t RESERVED10[5];

    union
    {
        __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */

        struct
        {
            __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
                                         *   = 1)                                                                      */
            __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
                                         *   LPOPTEN bit = 1)                                                          */
            uint8_t : 6;
        } IELEN_b;
    };
    __IM uint8_t  RESERVED11;
    __IM uint16_t RESERVED12;
    __IM uint32_t RESERVED13[15];

    union
    {
        __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */

        struct
        {
            __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
            uint16_t            : 7;
        } SELSR0_b;
    };
    __IM uint16_t RESERVED14;
    __IM uint32_t RESERVED15[31];

    union
    {
        __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */

        struct
        {
            __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
            uint32_t            : 7;
            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
                                        *   IR flag is prohibited.                                                    */
            uint32_t : 15;
        } DELSR_b[8];
    };
    __IM uint32_t RESERVED16[24];

    union
    {
        __IOM uint32_t IELSR[64];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..63]                    */

        struct
        {
            __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
                                        *   signal to be linked .                                                     */
            uint32_t            : 7;
            __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
            uint32_t            : 7;
            __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
            uint32_t            : 7;
        } IELSR_b[64];
    };
} R_ICU_Type;                          /*!< Size = 1024 (0x400)                                                       */

/* =========================================================================================================================== */
/* ================                                          R_IIC0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief I2C Bus Interface (R_IIC0)
 */

typedef struct                         /*!< (@ 0x4009F000) R_IIC0 Structure                                           */
{
    union
    {
        __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */

        struct
        {
            __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
            __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
            __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
            __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
            __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
            __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
            __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
                                        *   is initiated using the IICRST bit for a bus hang-up occurred
                                        *   during communication with the master device in slave mode,
                                        *   the states may become different between the slave device
                                        *   and the master device (due to the difference in the bit
                                        *   counter information).                                                     */
            __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
        } ICCR1_b;
    };

    union
    {
        __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */

        struct
        {
            uint8_t          : 1;
            __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
                                        *   condition issuance request) when the BBSY flag is set to
                                        *   0 (bus free state).                                                       */
            __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
                                        *   RS bit to 1 while issuing a stop condition.                               */
            __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
                                        *   bit is not possible while the setting of the BBSY flag
                                        *   is 0 (bus free state).Note: Do not set the SP bit to 1
                                        *   while a restart condition is being issued.                                */
            uint8_t            : 1;
            __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
            __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
            __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
        } ICCR2_b;
    };

    union
    {
        __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */

        struct
        {
            __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
            __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
            __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
                                        *   / 2^CKS )                                                                 */
            __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
        } ICMR1_b;
    };

    union
    {
        __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */

        struct
        {
            __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
            __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
            __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
            uint8_t            : 1;
            __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
            __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
        } ICMR2_b;
    };

    union
    {
        __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */

        struct
        {
            __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
            __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
            __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
            __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
            __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
            __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
                                        *   be sure to read the ICDRR beforehand.                                     */
            __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
        } ICMR3_b;
    };

    union
    {
        __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */

        struct
        {
            __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
            __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
            __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
            __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
            __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
            __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
            __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
            __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
        } ICFER_b;
    };

    union
    {
        __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */

        struct
        {
            __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
            __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
            __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
            __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
            uint8_t             : 1;
            __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
            uint8_t             : 1;
            __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
        } ICSER_b;
    };

    union
    {
        __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */

        struct
        {
            __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
            __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
            __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
            __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
            __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
            __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
            __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
            __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
        } ICIER_b;
    };

    union
    {
        __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */

        struct
        {
            __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
            __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
            __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
            __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
            uint8_t            : 1;
            __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
            uint8_t            : 1;
            __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
        } ICSR1_b;
    };

    union
    {
        __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */

        struct
        {
            __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
            __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
            __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
            __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
            __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
            __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
            __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
            __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
        } ICSR2_b;
    };
    __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */

    union
    {
        __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */

        struct
        {
            __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
            uint8_t           : 3;
        } ICBRL_b;
    };

    union
    {
        __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */

        struct
        {
            __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
            uint8_t           : 3;
        } ICBRH_b;
    };

    union
    {
        __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */

        struct
        {
            __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
        } ICDRT_b;
    };

    union
    {
        __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */

        struct
        {
            __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
        } ICDRR_b;
    };
    __IM uint8_t RESERVED[2];

    union
    {
        __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */

        struct
        {
            __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
            uint8_t             : 3;
            __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
            __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
            __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
            __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
        } ICWUR_b;
    };

    union
    {
        __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */

        struct
        {
            __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
            __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
            __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
            uint8_t              : 5;
        } ICWUR2_b;
    };
} R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_IRDA                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief IrDA Interface (R_IRDA)
 */

typedef struct                         /*!< (@ 0x40118F00) R_IRDA Structure                                           */
{
    union
    {
        __IOM uint8_t IRCR;            /*!< (@ 0x00000000) IrDA Control Register                                      */

        struct
        {
            uint8_t               : 2;
            __IOM uint8_t IRRXINV : 1; /*!< [2..2] IRRXD Polarity Switching                                           */
            __IOM uint8_t IRTXINV : 1; /*!< [3..3] IRTXD Polarity Switching                                           */
            uint8_t               : 3;
            __IOM uint8_t IRE     : 1; /*!< [7..7] IrDA Enable                                                        */
        } IRCR_b;
    };
} R_IRDA_Type;                         /*!< Size = 1 (0x1)                                                            */

/* =========================================================================================================================== */
/* ================                                          R_IWDT                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Independent Watchdog Timer (R_IWDT)
 */

typedef struct                         /*!< (@ 0x40083200) R_IWDT Structure                                           */
{
    union
    {
        __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */

        struct
        {
            __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
                                        *   0xFF to this register.                                                    */
        } IWDTRR_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */

        struct
        {
            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
            uint16_t            : 2;
            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
            uint16_t            : 2;
            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
            uint16_t            : 2;
        } IWDTCR_b;
    };

    union
    {
        __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */

        struct
        {
            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
        } IWDTSR_b;
    };

    union
    {
        __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */

        struct
        {
            uint8_t               : 7;
            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
        } IWDTRCR_b;
    };
    __IM uint8_t RESERVED1;

    union
    {
        __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */

        struct
        {
            uint8_t              : 7;
            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
        } IWDTCSTPR_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;
} R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */

/* =========================================================================================================================== */
/* ================                                          R_I3C0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief I3C Bus Interface (R_I3C0)
 */

typedef struct                         /*!< (@ 0x4011F000) R_I3C0 Structure                                           */
{
    union
    {
        __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */

        struct
        {
            __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
            uint32_t             : 31;
        } PRTS_b;
    };
    __IM uint32_t RESERVED[3];

    union
    {
        __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */

        struct
        {
            __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
            uint32_t            : 31;
        } CECTL_b;
    };

    union
    {
        __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */

        struct
        {
            __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
            uint32_t                : 6;
            __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
            __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
            uint32_t                : 20;
            __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
            __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
            __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
        } BCTL_b;
    };

    union
    {
        __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */

        struct
        {
            uint32_t              : 16;
            __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
            uint32_t              : 8;
            __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
        } MSDVAD_b;
    };
    __IM uint32_t RESERVED1;

    union
    {
        __IOM uint32_t RSTCTL;           /*!< (@ 0x00000020) Reset Control Register                                     */

        struct
        {
            __IOM uint32_t RI3CRST  : 1; /*!< [0..0] I3C Software Reset                                                 */
            __IOM uint32_t CMDQRST  : 1; /*!< [1..1] Command Queue Software Reset                                       */
            __IOM uint32_t RSPQRST  : 1; /*!< [2..2] Response Queue Software Reset                                      */
            __IOM uint32_t TDBRST   : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
            __IOM uint32_t RDBRST   : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
            __IOM uint32_t IBIQRST  : 1; /*!< [5..5] IBI Queue Software Reset                                           */
            __IOM uint32_t RSQRST   : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
            uint32_t                : 2;
            __IOM uint32_t HCMDQRST : 1; /*!< [9..9] High Priority Command Queue Software Reset                         */
            __IOM uint32_t HRSPQRST : 1; /*!< [10..10] High Priority Response Queue Software Rese                       */
            __IOM uint32_t HTDBRST  : 1; /*!< [11..11] High Priority Tx Data Buffer Software Reset                      */
            __IOM uint32_t HRDBRST  : 1; /*!< [12..12] High Priority Rx Data Buffer Software Reset                      */
            uint32_t                : 3;
            __IOM uint32_t INTLRST  : 1; /*!< [16..16] Internal Software Reset                                          */
            uint32_t                : 15;
        } RSTCTL_b;
    };

    union
    {
        __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */

        struct
        {
            uint32_t              : 2;
            __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
            uint32_t              : 1;
            __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
            uint32_t              : 2;
            __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
            uint32_t              : 24;
        } PRSST_b;
    };
    __IM uint32_t RESERVED2[2];

    union
    {
        __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */

        struct
        {
            uint32_t            : 10;
            __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
            uint32_t            : 21;
        } INST_b;
    };

    union
    {
        __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */

        struct
        {
            uint32_t            : 10;
            __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
            uint32_t            : 21;
        } INSTE_b;
    };

    union
    {
        __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */

        struct
        {
            uint32_t             : 10;
            __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
            uint32_t             : 21;
        } INIE_b;
    };

    union
    {
        __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */

        struct
        {
            uint32_t            : 10;
            __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
            uint32_t            : 21;
        } INSTFC_b;
    };
    __IM uint32_t RESERVED3;

    union
    {
        __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */

        struct
        {
            uint32_t          : 19;
            __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
            uint32_t          : 8;
        } DVCT_b;
    };
    __IM uint32_t RESERVED4[4];

    union
    {
        __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */

        struct
        {
            __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
            __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
            uint32_t                : 1;
            __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
            uint32_t                : 28;
        } IBINCTL_b;
    };
    __IM uint32_t RESERVED5;

    union
    {
        __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */

        struct
        {
            __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
            __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
            __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
            uint32_t              : 5;
            __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
            uint32_t              : 3;
            __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
            uint32_t              : 1;
            __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
            __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
            uint32_t              : 16;
        } BFCTL_b;
    };

    union
    {
        __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */

        struct
        {
            __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
            uint32_t             : 4;
            __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
            __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
            uint32_t             : 8;
            __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
            __IOM uint32_t SVAEn : 3;  /*!< [18..16] Slave Address Enable                                             */
            uint32_t             : 13;
        } SVCTL_b;
    };
    __IM uint32_t RESERVED6[2];

    union
    {
        __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */

        struct
        {
            __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
            uint32_t               : 29;
        } REFCKCTL_b;
    };

    union
    {
        __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */

        struct
        {
            __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
            __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
            __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
            uint32_t              : 2;
            __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
            uint32_t              : 1;
            __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
        } STDBR_b;
    };

    union
    {
        __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */

        struct
        {
            __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
            __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
            __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
            uint32_t             : 2;
            __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate High-Level Period Push-Pull                    */
            uint32_t             : 2;
        } EXTBR_b;
    };

    union
    {
        __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */

        struct
        {
            __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
            uint32_t              : 23;
        } BFRECDT_b;
    };

    union
    {
        __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */

        struct
        {
            __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
            uint32_t              : 23;
        } BAVLCDT_b;
    };

    union
    {
        __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */

        struct
        {
            __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
            uint32_t              : 14;
        } BIDLCDT_b;
    };

    union
    {
        __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */

        struct
        {
            __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
            __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
            __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
            uint32_t              : 1;
            __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
            uint32_t              : 3;
            __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
            uint32_t              : 4;
            __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
            uint32_t              : 16;
        } OUTCTL_b;
    };

    union
    {
        __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */

        struct
        {
            __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
            __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
            uint32_t            : 27;
        } INCTL_b;
    };

    union
    {
        __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */

        struct
        {
            __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
            uint32_t              : 2;
            __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
            __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
            __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
            uint32_t              : 24;
        } TMOCTL_b;
    };
    __IM uint32_t RESERVED7;

    union
    {
        __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */

        struct
        {
            __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
            uint32_t               : 3;
            __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
            uint32_t               : 1;
            __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
            __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
            uint32_t               : 24;
        } WUCTL_b;
    };
    __IM uint32_t RESERVED8;

    union
    {
        __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */

        struct
        {
            __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
            __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
            __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
            uint32_t              : 29;
        } ACKCTL_b;
    };

    union
    {
        __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */

        struct
        {
            __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
            __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
            uint32_t              : 30;
        } SCSTRCTL_b;
    };
    __IM uint32_t RESERVED9[2];

    union
    {
        __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */

        struct
        {
            __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
            uint32_t              : 12;
            __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
            __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
            __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
            __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
        } SCSTLCTL_b;
    };
    __IM uint32_t RESERVED10[3];

    union
    {
        __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */

        struct
        {
            uint32_t             : 16;
            __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
        } SVTDLG0_b;
    };
    __IM uint32_t RESERVED11[23];

    union
    {
        __IOM uint32_t STCTL;          /*!< (@ 0x00000120) Synchronous Timing Control Register                        */

        struct
        {
            __IOM uint32_t STOE : 1;   /*!< [0..0] Synchronous Timing output Enable                                   */
            uint32_t            : 31;
        } STCTL_b;
    };

    union
    {
        __IOM uint32_t ATCTL;          /*!< (@ 0x00000124) Asynchronous Timing Control Register                       */

        struct
        {
            __IOM uint32_t ATTRGS : 1; /*!< [0..0] Asynchronous Timing Trigger Select                                 */
            __IOM uint32_t MREFOE : 1; /*!< [1..1] MREF Output Enable (Capture Event / Counter Overflow)              */
            __IOM uint32_t AMEOE  : 1; /*!< [2..2] Additional Master-initiated bus Event Output Enable                */
            uint32_t              : 5;
            __IOM uint32_t CDIV   : 8; /*!< [15..8] TCLK Counter Divide Setting                                       */
            uint32_t              : 16;
        } ATCTL_b;
    };

    union
    {
        __IOM uint32_t ATTRG;          /*!< (@ 0x00000128) Asynchronous Timing Trigger Register                       */

        struct
        {
            __OM uint32_t ATSTRG : 1;  /*!< [0..0] Asynchronous Timing Software Trigger                               */
            uint32_t             : 31;
        } ATTRG_b;
    };

    union
    {
        __IOM uint32_t ATCCNTE;        /*!< (@ 0x0000012C) Asynchronous Timing Contorol Counter enable Register       */

        struct
        {
            __IOM uint32_t ATCE : 1;   /*!< [0..0] Asynchronous Timing Counter Enable for MREF, MC2, SC1,
                                        *   SC2.                                                                      */
            uint32_t : 31;
        } ATCCNTE_b;
    };
    __IM uint32_t RESERVED12[4];

    union
    {
        __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */

        struct
        {
            __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
            __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
            __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
            uint32_t             : 29;
        } CNDCTL_b;
    };
    __IM uint32_t  RESERVED13[3];
    __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
    __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
    __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
    __IM uint32_t  RESERVED14[8];
    __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
    __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */

    union
    {
        __OM uint32_t HCMDQP;          /*!< (@ 0x00000184) High Priority Command Queue Port Register                  */

        struct
        {
            __OM uint32_t HCMDQP : 32; /*!< [31..0] High Priority Command Queue Port                                  */
        } HCMDQP_b;
    };

    union
    {
        __IM uint32_t HRSPQP;          /*!< (@ 0x00000188) High Priority Response Queue Port Register                 */

        struct
        {
            __IM uint32_t HRSPQP : 32; /*!< [31..0] High Priority Response Queue Port                                 */
        } HRSPQP_b;
    };

    union
    {
        __IOM uint32_t HTDTBP;          /*!< (@ 0x0000018C) High Priority Transfer Data Buffer Port Register           */

        struct
        {
            __IOM uint32_t HTDTBP : 32; /*!< [31..0] High Priority Transfer Data Buffer Port                           */
        } HTDTBP_b;
    };

    union
    {
        __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */

        struct
        {
            __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
            __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
            __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
            __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
        } NQTHCTL_b;
    };

    union
    {
        __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
                                        *                  Register 0                                                 */

        struct
        {
            __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
            uint32_t              : 5;
            __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
            uint32_t              : 5;
            __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
            uint32_t              : 5;
            __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
            uint32_t              : 5;
        } NTBTHCTL0_b;
    };
    __IM uint32_t RESERVED15[10];

    union
    {
        __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
                                        *                  Register                                                   */

        struct
        {
            __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
            uint32_t             : 24;
        } NRQTHCTL_b;
    };

    union
    {
        __IOM uint32_t HQTHCTL;        /*!< (@ 0x000001C4) High Priority Queue Threshold Control Register             */

        struct
        {
            __IOM uint32_t CMDQTH : 8; /*!< [7..0] High Priority Command Queue Threshold                              */
            __IOM uint32_t RSPQTH : 8; /*!< [15..8] High Priority Response Queue Threshold                            */
            uint32_t              : 16;
        } HQTHCTL_b;
    };

    union
    {
        __IOM uint32_t HTBTHCTL;       /*!< (@ 0x000001C8) High Priority Transfer Data Buffer Threshold
                                        *                  Control Register                                           */

        struct
        {
            __IOM uint32_t TXDBTH : 3; /*!< [2..0] High Priority Tx Data Buffer Threshold                             */
            uint32_t              : 5;
            __IOM uint32_t RXDBTH : 3; /*!< [10..8] High Priority Rx Data Buffer Threshold                            */
            uint32_t              : 5;
            __IOM uint32_t TXSTTH : 3; /*!< [18..16] High Priority Tx Start Threshold                                 */
            uint32_t              : 5;
            __IOM uint32_t RXSTTH : 3; /*!< [26..24] High Priority Rx Start Threshold                                 */
            uint32_t              : 5;
        } HTBTHCTL_b;
    };
    __IM uint32_t RESERVED16;

    union
    {
        __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */

        struct
        {
            __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
            __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
            __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
            uint32_t               : 1;
            __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
            uint32_t               : 3;
            __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
            uint32_t               : 7;
            __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
            uint32_t               : 3;
            __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
            uint32_t               : 3;
            __IOM uint32_t WUCNDDF : 1; /*!< [24..24] Wake-Up Condition Detection Flag                                 */
            uint32_t               : 7;
        } BST_b;
    };

    union
    {
        __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */

        struct
        {
            __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
            __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
            __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
            uint32_t               : 1;
            __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
            uint32_t               : 3;
            __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
            uint32_t               : 7;
            __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
            uint32_t               : 3;
            __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
            uint32_t               : 3;
            __IOM uint32_t WUCNDDE : 1; /*!< [24..24] Wake-up Condition Detection Enable                               */
            uint32_t               : 7;
        } BSTE_b;
    };

    union
    {
        __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */

        struct
        {
            __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
            __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
            __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
            uint32_t                : 1;
            __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
            uint32_t                : 3;
            __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
            uint32_t                : 7;
            __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
            uint32_t                : 3;
            __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
            uint32_t                : 3;
            __IOM uint32_t WUCNDDIE : 1; /*!< [24..24] Wake-Up Condition Detection Interrupt Enable                     */
            uint32_t                : 7;
        } BIE_b;
    };

    union
    {
        __IOM uint32_t BSTFC;            /*!< (@ 0x000001DC) Bus Status Force Register                                  */

        struct
        {
            __OM uint32_t STCNDDFC  : 1; /*!< [0..0] START condition Detection Force                                    */
            __OM uint32_t SPCNDDFC  : 1; /*!< [1..1] STOP condition Detection Force                                     */
            __OM uint32_t HDREXDFC  : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
            uint32_t                : 1;
            __OM uint32_t NACKDFC   : 1; /*!< [4..4] NACK Detection Force                                               */
            uint32_t                : 3;
            __OM uint32_t TENDFC    : 1; /*!< [8..8] Transmit End Force                                                 */
            uint32_t                : 7;
            __OM uint32_t ALFC      : 1; /*!< [16..16] Arbitration Lost Force                                           */
            uint32_t                : 3;
            __OM uint32_t TODFC     : 1; /*!< [20..20] Timeout Detection Force                                          */
            uint32_t                : 3;
            __IOM uint32_t WUCNDDFC : 1; /*!< [24..24] Wake-Up Condition Detection Force                                */
            uint32_t                : 7;
        } BSTFC_b;
    };

    union
    {
        __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */

        struct
        {
            __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
            __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
            __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
            __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
            __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
            __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
            uint32_t               : 3;
            __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
            uint32_t               : 10;
            __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
            uint32_t               : 11;
        } NTST_b;
    };

    union
    {
        __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */

        struct
        {
            __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
            __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
            __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
            __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
            __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
            __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
            uint32_t               : 3;
            __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
            uint32_t               : 10;
            __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
            uint32_t               : 11;
        } NTSTE_b;
    };

    union
    {
        __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */

        struct
        {
            __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
            __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
            __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
            __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
            __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
            __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
            uint32_t                : 3;
            __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
            uint32_t                : 10;
            __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
            uint32_t                : 11;
        } NTIE_b;
    };

    union
    {
        __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */

        struct
        {
            __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
            __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
            __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
            __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
            __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
            __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
            uint32_t               : 3;
            __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
            uint32_t               : 10;
            __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
            uint32_t               : 11;
        } NTSTFC_b;
    };
    __IM uint32_t RESERVED17[4];

    union
    {
        __IOM uint32_t HTST;           /*!< (@ 0x00000200) High Priority Transfer Status Register                     */

        struct
        {
            __IOM uint32_t TDBEF  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Flag                            */
            __IOM uint32_t RDBFF  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Flag                             */
            uint32_t              : 1;
            __IOM uint32_t CMDQEF : 1; /*!< [3..3] High Priority Command Queue Empty Flag                             */
            __IOM uint32_t RSPQFF : 1; /*!< [4..4] High Priority Response Queue Full Flag                             */
            __IOM uint32_t TABTF  : 1; /*!< [5..5] High Priority Transfer Abort Flag                                  */
            uint32_t              : 3;
            __IOM uint32_t TEF    : 1; /*!< [9..9] High Priority Transfer Error Flag                                  */
            uint32_t              : 22;
        } HTST_b;
    };

    union
    {
        __IOM uint32_t HTSTE;          /*!< (@ 0x00000204) High Priority Transfer Status Enable Register              */

        struct
        {
            __IOM uint32_t TDBEE  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Enable                          */
            __IOM uint32_t RDBFE  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Enable                           */
            uint32_t              : 1;
            __IOM uint32_t CMDQEE : 1; /*!< [3..3] High Priority Command Queue Empty Enable                           */
            __IOM uint32_t RSPQFE : 1; /*!< [4..4] High Priority Response Queue Full Enable                           */
            __IOM uint32_t TABTE  : 1; /*!< [5..5] High Priority Transfer Abort Enable                                */
            uint32_t              : 3;
            __IOM uint32_t TEE    : 1; /*!< [9..9] High Priority Transfer Error Enable                                */
            uint32_t              : 22;
        } HTSTE_b;
    };

    union
    {
        __IOM uint32_t HTIE;            /*!< (@ 0x00000208) High Priority Transfer Interrupt Enable Register           */

        struct
        {
            __IOM uint32_t TDBEIE  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Interrupt Enable                */
            __IOM uint32_t RDBFIE  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Interrupt Enable                 */
            uint32_t               : 1;
            __IOM uint32_t CMDQEIE : 1; /*!< [3..3] High Priority Command Queue Empty Interrupt Enable                 */
            __IOM uint32_t RSPQFIE : 1; /*!< [4..4] High Priority Response Queue Full Interrupt Enable                 */
            __IOM uint32_t TABTIE  : 1; /*!< [5..5] High Priority Transfer Abort Interrupt Enable                      */
            uint32_t               : 3;
            __IOM uint32_t TEIE    : 1; /*!< [9..9] High Priority Transfer Error Interrupt Enable                      */
            uint32_t               : 22;
        } HTIE_b;
    };

    union
    {
        __IOM uint32_t HTSTFC;         /*!< (@ 0x0000020C) High Priority Transfer Status Force Register               */

        struct
        {
            __OM uint32_t TDBEFC  : 1; /*!< [0..0] High Priority Tx Data Buffer Empty Force                           */
            __OM uint32_t RDBFFC  : 1; /*!< [1..1] High Priority Rx Data Buffer Full Force                            */
            uint32_t              : 1;
            __OM uint32_t CMDQEFC : 1; /*!< [3..3] High Priority Command Queue Empty Force                            */
            __OM uint32_t RSPQFFC : 1; /*!< [4..4] High Priority Response Queue Full Force                            */
            __OM uint32_t TABTFC  : 1; /*!< [5..5] High Priority Transfer Abort Force                                 */
            uint32_t              : 3;
            __OM uint32_t TEFC    : 1; /*!< [9..9] High Priority Transfer Error Force                                 */
            uint32_t              : 22;
        } HTSTFC_b;
    };

    union
    {
        __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */

        struct
        {
            __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
            __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
            __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
            uint32_t            : 29;
        } BCST_b;
    };

    union
    {
        __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */

        struct
        {
            __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
            uint32_t             : 4;
            __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
            __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
            uint32_t             : 8;
            __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
            __IOM uint32_t SVAFn : 3;  /*!< [18..16] Slave Address Detection Flag                                     */
            uint32_t             : 13;
        } SVST_b;
    };

    union
    {
        __IM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Operating Status Register                     */

        struct
        {
            __IM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
            uint32_t              : 31;
        } WUST_b;
    };

    union
    {
        __IM uint32_t MRCCPT;          /*!< (@ 0x0000021C) MsyncCNT Counter Capture Register                          */

        struct
        {
            __IM uint32_t MRCCPT : 32; /*!< [31..0] MSyncCNT Counter Capture                                          */
        } MRCCPT_b;
    };
    __IM uint32_t RESERVED18;

    union
    {
        __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS0_b;
    };
    __IM uint32_t RESERVED19;

    union
    {
        __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS1_b;
    };
    __IM uint32_t RESERVED20;

    union
    {
        __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS2_b;
    };
    __IM uint32_t RESERVED21;

    union
    {
        __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS3_b;
    };
    __IM uint32_t RESERVED22;

    union
    {
        __IOM uint32_t DATBAS4;         /*!< (@ 0x00000244) Device Address Table Basic Register 4                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS4_b;
    };
    __IM uint32_t RESERVED23;

    union
    {
        __IOM uint32_t DATBAS5;         /*!< (@ 0x0000024C) Device Address Table Basic Register 5                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS5_b;
    };
    __IM uint32_t RESERVED24;

    union
    {
        __IOM uint32_t DATBAS6;         /*!< (@ 0x00000254) Device Address Table Basic Register 6                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS6_b;
    };
    __IM uint32_t RESERVED25;

    union
    {
        __IOM uint32_t DATBAS7;         /*!< (@ 0x0000025C) Device Address Table Basic Register 7                      */

        struct
        {
            __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
            uint32_t               : 5;
            __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
            __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
            __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
            __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
            __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
            uint32_t               : 5;
            __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
            __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
        } DATBAS7_b;
    };
    __IM uint32_t RESERVED26[16];

    union
    {
        __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */

        struct
        {
            __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
            uint32_t              : 9;
            __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
            uint32_t              : 5;
            __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
            __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
        } EXDATBAS_b;
    };
    __IM uint32_t RESERVED27[3];

    union
    {
        __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */

        struct
        {
            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
            uint32_t               : 1;
            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
            uint32_t               : 3;
            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
            uint32_t               : 9;
        } SDATBAS0_b;
    };

    union
    {
        __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */

        struct
        {
            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
            uint32_t               : 1;
            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
            uint32_t               : 3;
            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
            uint32_t               : 9;
        } SDATBAS1_b;
    };

    union
    {
        __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */

        struct
        {
            __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
            __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
            uint32_t               : 1;
            __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
            uint32_t               : 3;
            __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
            uint32_t               : 9;
        } SDATBAS2_b;
    };
    __IM uint32_t RESERVED28[5];

    union
    {
        __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT0_b;
    };

    union
    {
        __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT1_b;
    };

    union
    {
        __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT2_b;
    };

    union
    {
        __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT3_b;
    };

    union
    {
        __IOM uint32_t MSDCT4;         /*!< (@ 0x000002E0) Master Device Characteristic Table Register 4              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT4_b;
    };

    union
    {
        __IOM uint32_t MSDCT5;         /*!< (@ 0x000002E4) Master Device Characteristic Table Register 5              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT5_b;
    };

    union
    {
        __IOM uint32_t MSDCT6;         /*!< (@ 0x000002E8) Master Device Characteristic Table Register 6              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT6_b;
    };

    union
    {
        __IOM uint32_t MSDCT7;         /*!< (@ 0x000002EC) Master Device Characteristic Table Register 7              */

        struct
        {
            uint32_t              : 8;
            __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t RBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t RBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } MSDCT7_b;
    };
    __IM uint32_t RESERVED29[12];

    union
    {
        __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */

        struct
        {
            __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
            __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
            __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
            __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
            __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
            __IOM uint32_t TBCR4  : 1; /*!< [12..12] Bridge Identifier                                                */
            __IOM uint32_t TBCR5  : 1; /*!< [13..13] SDR Only / SDR and HDR Capable                                   */
            __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
            uint32_t              : 16;
        } SVDCT_b;
    };
    __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
                                        *                  ID Low Register                                            */
    __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
                                        *                  ID High Register                                           */
    __IM uint32_t RESERVED30;

    union
    {
        __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */

        struct
        {
            uint32_t             : 16;
            __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
            uint32_t             : 1;
            __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
            uint32_t             : 2;
            __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
            __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
        } SVDVAD0_b;
    };

    union
    {
        __IM uint32_t SVDVAD1;         /*!< (@ 0x00000334) Slave Device Address Register 1                            */

        struct
        {
            uint32_t             : 16;
            __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
            uint32_t             : 1;
            __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
            uint32_t             : 2;
            __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
            __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
        } SVDVAD1_b;
    };

    union
    {
        __IM uint32_t SVDVAD2;         /*!< (@ 0x00000338) Slave Device Address Register 2                            */

        struct
        {
            uint32_t             : 16;
            __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
            uint32_t             : 1;
            __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
            uint32_t             : 2;
            __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
            __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
        } SVDVAD2_b;
    };
    __IM uint32_t RESERVED31[5];

    union
    {
        __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */

        struct
        {
            __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
            __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
            uint32_t              : 1;
            __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
            uint32_t              : 28;
        } CSECMD_b;
    };

    union
    {
        __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */

        struct
        {
            __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
            uint32_t             : 28;
        } CEACTST_b;
    };

    union
    {
        __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */

        struct
        {
            __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
            uint32_t            : 16;
        } CMWLG_b;
    };

    union
    {
        __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */

        struct
        {
            __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
            __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
            uint32_t              : 8;
        } CMRLG_b;
    };

    union
    {
        __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */

        struct
        {
            __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
            uint32_t            : 24;
        } CETSTMD_b;
    };

    union
    {
        __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */

        struct
        {
            __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
            uint32_t              : 1;
            __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
            __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
            __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
            uint32_t              : 16;
        } CGDVST_b;
    };

    union
    {
        __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */

        struct
        {
            __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
            uint32_t             : 29;
        } CMDSPW_b;
    };

    union
    {
        __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */

        struct
        {
            __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
            __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
            uint32_t              : 26;
        } CMDSPR_b;
    };

    union
    {
        __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */

        struct
        {
            __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
            uint32_t              : 7;
            __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
        } CMDSPT_b;
    };

    union
    {
        __IOM uint32_t CETSM;            /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
                                          *                  Register                                                   */

        struct
        {
            __IOM uint32_t SPTSYN   : 1; /*!< [0..0] Supports Sync Mode                                                 */
            __IOM uint32_t SPTASYN0 : 1; /*!< [1..1] Support Async Mode 0                                               */
            __IOM uint32_t SPTASYN1 : 1; /*!< [2..2] Support Async Mode 1                                               */
            uint32_t                : 5;
            __IOM uint32_t FREQ     : 8; /*!< [15..8] Frequency Byte                                                    */
            __IOM uint32_t INAC     : 8; /*!< [23..16] Inaccuracy Byte                                                  */
            uint32_t                : 8;
        } CETSM_b;
    };

    union
    {
        __IOM uint32_t CETSS;          /*!< (@ 0x00000378) CCC Exchange Timing Support Information S (State)
                                        *                  Register                                                   */

        struct
        {
            __IOM uint32_t SYNE  : 1;  /*!< [0..0] Sync Mode Enabled                                                  */
            __IOM uint32_t ASYNE : 2;  /*!< [2..1] Async Mode Enabled                                                 */
            uint32_t             : 4;
            __IOM uint32_t ICOVF : 1;  /*!< [7..7] Internal Counter Overflow                                          */
            uint32_t             : 24;
        } CETSS_b;
    };

    union
    {
        __IOM uint32_t CGHDRCAP;       /*!< (@ 0x0000037C) CCC Get HDR Capability Register                            */

        struct
        {
            __IOM uint32_t DDREN : 1;  /*!< [0..0] HDR-DDR Operation Enable                                           */
            __IOM uint32_t TSPEN : 1;  /*!< [1..1] HDR-TSP Operation Enable                                           */
            __IOM uint32_t TSLEN : 1;  /*!< [2..2] HDR-TSL Operation Enable                                           */
            uint32_t             : 29;
        } CGHDRCAP_b;
    };

    union
    {
        __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */

        struct
        {
            __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
            uint32_t             : 2;
            __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
            uint32_t             : 24;
        } BITCNT_b;
    };
    __IM uint32_t RESERVED32[4];

    union
    {
        __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */

        struct
        {
            __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
            __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
            __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
            __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
            uint32_t              : 3;
        } NQSTLV_b;
    };

    union
    {
        __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register 0                 */

        struct
        {
            __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
            __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
            uint32_t             : 16;
        } NDBSTLV0_b;
    };
    __IM uint32_t RESERVED33[9];

    union
    {
        __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */

        struct
        {
            __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
            uint32_t            : 24;
        } NRSQSTLV_b;
    };

    union
    {
        __IM uint32_t HQSTLV;          /*!< (@ 0x000003C4) High Priority Queue Status Level Register                  */

        struct
        {
            __IM uint32_t CMDQLV : 8;  /*!< [7..0] High Priority Command Queue Level                                  */
            __IM uint32_t RSPQLV : 8;  /*!< [15..8] High Priority Response Queue Level                                */
            uint32_t             : 16;
        } HQSTLV_b;
    };

    union
    {
        __IM uint32_t HDBSTLV;         /*!< (@ 0x000003C8) High Priority Data Buffer Status Level Register            */

        struct
        {
            __IM uint32_t TDBFLV : 8;  /*!< [7..0] High Priority Tx Data Buffer Free Level                            */
            __IM uint32_t RDBLV  : 8;  /*!< [15..8] High Priority Rx Data Buffer Level                                */
            uint32_t             : 16;
        } HDBSTLV_b;
    };

    union
    {
        __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */

        struct
        {
            __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
            __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
            __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
            __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
            uint32_t            : 28;
        } PRSTDBG_b;
    };

    union
    {
        __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */

        struct
        {
            __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
            uint32_t             : 24;
        } MSERRCNT_b;
    };
    __IM uint32_t RESERVED34[3];

    union
    {
        __IM uint32_t SC1CPT;          /*!< (@ 0x000003E0) SC1 Capture monitor Register                               */

        struct
        {
            __IM uint32_t SC1C : 16;   /*!< [15..0] SC1 Capture                                                       */
            uint32_t           : 16;
        } SC1CPT_b;
    };

    union
    {
        __IM uint32_t SC2CPT;          /*!< (@ 0x000003E4) SC2 Capture monitor Register                               */

        struct
        {
            __IM uint32_t SC2C : 16;   /*!< [15..0] SC2 Capture                                                       */
            uint32_t           : 16;
        } SC2CPT_b;
    };
} R_I3C0_Type;                         /*!< Size = 1000 (0x3e8)                                                       */

/* =========================================================================================================================== */
/* ================                                        R_MPU_MMPU                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief Bus Master MPU (R_MPU_MMPU)
 */

typedef struct                         /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
{
    union
    {
        __IOM uint16_t OAD;            /*!< (@ 0x00000000) MMPU Operation After Detection Register                    */

        struct
        {
            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
            uint16_t           : 7;
            __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
                                        *   stored.                                                                   */
        } OAD_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t OADPT;           /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register            */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
                                         *   stored.                                                                   */
        } OADPT_b;
    };
    __IM uint16_t               RESERVED1;
    __IM uint32_t               RESERVED2[62];
    __IOM R_MPU_MMPU_GROUP_Type DMAC0;    /*!< (@ 0x00000100) DMAC0 MMPU Registers                                       */
    __IOM R_MPU_MMPU_GROUP_Type DMAC1;    /*!< (@ 0x00000300) DMAC1 MMPU Registers                                       */
    __IOM R_MPU_MMPU_GROUP_Type EDMAC;    /*!< (@ 0x00000500) EDMAC MMPU Registers                                       */
    __IOM R_MPU_MMPU_GROUP_Type GLCDC;    /*!< (@ 0x00000700) GLCDC MMPU Registers                                       */
    __IOM R_MPU_MMPU_GROUP_Type DRW;      /*!< (@ 0x00000900) DRW MMPU Registers                                         */
    __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers                                    */
    __IOM R_MPU_MMPU_GROUP_Type CEU;      /*!< (@ 0x00000D00) CEU MMPU Registers                                         */
} R_MPU_MMPU_Type;                        /*!< Size = 3840 (0xf00)                                                       */

/* =========================================================================================================================== */
/* ================                                        R_MPU_SPMON                                        ================ */
/* =========================================================================================================================== */

/**
 * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
 */

typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
{
    __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
} R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_MSTP                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief System-Module Stop (R_MSTP)
 */

typedef struct                          /*!< (@ 0x40084000) R_MSTP Structure                                           */
{
    union
    {
        __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */

        struct
        {
            __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
            __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
                                         *   usage.                                                                    */
        } MSTPCRA_b;
    };

    union
    {
        __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */

        struct
        {
            __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
            __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
                                         *   usage.                                                                    */
        } MSTPCRB_b;
    };

    union
    {
        __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */

        struct
        {
            __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
            __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
                                         *   usage.                                                                    */
        } MSTPCRC_b;
    };

    union
    {
        __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */

        struct
        {
            __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
            __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
                                         *   usage.                                                                    */
            __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
                                         *   usage.                                                                    */
        } MSTPCRD_b;
    };

    union
    {
        union
        {
            __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */

            struct
            {
                __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
                __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
                                             *   usage.                                                                    */
                __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
                                             *   usage.                                                                    */
            } MSTPCRE_b;
        };

        union
        {
            __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */

            struct
            {
                __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
                __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
                __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
                uint16_t                : 4;
                __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
                __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
            } LSMRWDIS_b;
        };
    };
} R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_PORT0                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief I/O Ports (R_PORT0)
 */

typedef struct                         /*!< (@ 0x4001F000) R_PORT0 Structure                                          */
{
    union
    {
        union
        {
            __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */

            struct
            {
                __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
                __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
            } PCNTR1_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */

                struct
                {
                    __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
                    __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
                    __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
                    __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
                    __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
                    __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
                    __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
                    __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
                    __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
                    __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
                    __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
                    __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
                    __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
                    __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
                    __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
                    __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
                } PODR_b;
            };

            union
            {
                __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */

                struct
                {
                    __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
                    __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
                    __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
                    __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
                    __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
                    __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
                    __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
                    __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
                    __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
                    __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
                    __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
                    __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
                    __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
                    __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
                    __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
                    __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
                } PDR_b;
            };
        };
    };

    union
    {
        union
        {
            __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */

            struct
            {
                __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
                __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
            } PCNTR2_b;
        };

        struct
        {
            union
            {
                __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */

                struct
                {
                    __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
                    __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
                    __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
                    __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
                    __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
                    __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
                    __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
                } EIDR_b;
            };

            union
            {
                __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */

                struct
                {
                    __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
                    __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
                    __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
                    __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
                    __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
                    __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
                    __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
                    __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
                    __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
                    __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
                    __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
                    __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
                    __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
                    __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
                    __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
                    __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
                } PIDR_b;
            };
        };
    };

    union
    {
        union
        {
            __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */

            struct
            {
                __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
                __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
            } PCNTR3_b;
        };

        struct
        {
            union
            {
                __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */

                struct
                {
                    __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
                    __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
                    __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
                    __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
                    __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
                    __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
                    __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
                    __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
                    __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
                    __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
                    __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
                    __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
                    __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
                    __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
                    __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
                    __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
                } PORR_b;
            };

            union
            {
                __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */

                struct
                {
                    __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
                    __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
                    __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
                    __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
                    __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
                    __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
                    __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
                    __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
                    __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
                    __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
                    __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
                    __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
                    __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
                    __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
                    __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
                    __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
                } POSR_b;
            };
        };
    };

    union
    {
        union
        {
            __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */

            struct
            {
                __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
                __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
            } PCNTR4_b;
        };

        struct
        {
            union
            {
                __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */

                struct
                {
                    __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
                    __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
                    __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
                    __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
                    __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
                    __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
                    __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
                } EORR_b;
            };

            union
            {
                __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */

                struct
                {
                    __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
                    __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
                    __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
                    __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
                    __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
                    __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
                    __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
                } EOSR_b;
            };
        };
    };
} R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */

/* =========================================================================================================================== */
/* ================                                           R_PFS                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief I/O Ports-PFS (R_PFS)
 */

typedef struct                         /*!< (@ 0x4001F800) R_PFS Structure                                            */
{
    __IOM R_PFS_PORT_Type PORT[15];    /*!< (@ 0x00000000) Port [0..14]                                               */
} R_PFS_Type;                          /*!< Size = 960 (0x3c0)                                                        */

/* =========================================================================================================================== */
/* ================                                          R_PMISC                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief I/O Ports-MISC (R_PMISC)
 */

typedef struct                         /*!< (@ 0x4001FD00) R_PMISC Structure                                          */
{
    __IM uint16_t RESERVED;
    __IM uint8_t  RESERVED1;

    union
    {
        __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */

        struct
        {
            uint8_t             : 6;
            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
        } PWPR_b;
    };
    __IM uint8_t RESERVED2;

    union
    {
        __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */

        struct
        {
            uint8_t             : 6;
            __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
            __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
        } PWPRS_b;
    };
    __IM uint16_t RESERVED3[3];

    union
    {
        __IOM uint8_t PRWCNTR;         /*!< (@ 0x0000000C) Port Read Wait Control Register                            */

        struct
        {
            __IOM uint8_t WAIT : 4;    /*!< [3..0] Wait Cycle Control                                                 */
            uint8_t            : 4;
        } PRWCNTR_b;
    };
    __IM uint8_t             RESERVED4;
    __IM uint16_t            RESERVED5;
    __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
    __IM uint16_t            RESERVED6[12];

    union
    {
        __IOM uint16_t PSAR;            /*!< (@ 0x00000040) PORT Security Attribution Register                         */

        struct
        {
            __IOM uint16_t PORTSA0 : 1; /*!< [0..0] PRWCNTR Security Attribution                                       */
            uint16_t               : 15;
        } PSAR_b;
    };
} R_PMISC_Type;                         /*!< Size = 66 (0x42)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_QSPI                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Quad Serial Peripheral Interface (R_QSPI)
 */

typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
{
    union
    {
        __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */

        struct
        {
            __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
            uint32_t              : 1;
            __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
            __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
            __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
                                        *   other than on byte boundaries                                             */
            __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
                                        *   input to CFGMD3.                                                          */
            __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
                                        *   the serial interface                                                      */
            __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
            __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
            uint32_t              : 3;
            __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
            uint32_t              : 16;
        } SFMSMD_b;
    };

    union
    {
        __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */

        struct
        {
            __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
            __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
            __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
            uint32_t              : 26;
        } SFMSSC_b;
    };

    union
    {
        __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */

        struct
        {
            __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
                                        *   to the irregularity.)NOTE: When PCLKA multiplied by an
                                        *   odd number is selected, the high-level width of the SCK
                                        *   signal is longer than the low-level width by 1 x PCLKA
                                        *   before duty ratio correction.                                             */
            __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
                                        *   SCK signal                                                                */
            uint32_t : 26;
        } SFMSKC_b;
    };

    union
    {
        __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */

        struct
        {
            __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
                                        *   (No combination other than the above is available.)                       */
            uint32_t            : 1;
            __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
            __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
            uint32_t            : 24;
        } SFMSST_b;
    };

    union
    {
        __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */

        struct
        {
            __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
                                        *   to and from this port is converted to a SPIbus cycle. This
                                        *   port is accessible in the direct communication mode (DCOM=1)
                                        *   only.Access to this port is ignored in the ROM access mode.               */
            uint32_t : 24;
        } SFMCOM_b;
    };

    union
    {
        __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */

        struct
        {
            __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
            uint32_t            : 31;
        } SFMCMD_b;
    };

    union
    {
        __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */

        struct
        {
            __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
            uint32_t             : 6;
            __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
                                        *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
                                        *   ignored.                                                                  */
            uint32_t : 24;
        } SFMCST_b;
    };
    __IM uint32_t RESERVED;

    union
    {
        __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */

        struct
        {
            __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
            uint32_t              : 24;
        } SFMSIC_b;
    };

    union
    {
        __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */

        struct
        {
            __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
            uint32_t              : 2;
            __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
                                        *   Interface address width is selected 4 bytes.                              */
            uint32_t : 27;
        } SFMSAC_b;
    };

    union
    {
        __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */

        struct
        {
            __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
                                        *   instructions                                                              */
            uint32_t              : 2;
            __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
            __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
            __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
            uint32_t              : 16;
        } SFMSDC_b;
    };
    __IM uint32_t RESERVED1;

    union
    {
        __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */

        struct
        {
            __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
                                        *   is required to be set by software separately.                             */
            uint32_t              : 2;
            __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
                                        *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
            uint32_t : 27;
        } SFMSPC_b;
    };

    union
    {
        __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */

        struct
        {
            uint32_t              : 2;
            __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
            uint32_t              : 29;
        } SFMPMD_b;
    };
    __IM uint32_t RESERVED2[499];

    union
    {
        __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */

        struct
        {
            uint32_t                : 26;
            __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
                                          *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
                                          *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
        } SFMCNT1_b;
    };
} R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */

/* =========================================================================================================================== */
/* ================                                           R_RTC                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Realtime Clock (R_RTC)
 */

typedef struct                         /*!< (@ 0x40083000) R_RTC Structure                                            */
{
    union
    {
        __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */

        struct
        {
            __IM uint8_t F64HZ  : 1;   /*!< [0..0] 64Hz Flag                                                          */
            __IM uint8_t F32HZ  : 1;   /*!< [1..1] 32Hz Flag                                                          */
            __IM uint8_t F16HZ  : 1;   /*!< [2..2] 16Hz Flag                                                          */
            __IM uint8_t F8HZ   : 1;   /*!< [3..3] 8Hz Flag                                                           */
            __IM uint8_t F4HZ   : 1;   /*!< [4..4] 4Hz Flag                                                           */
            __IM uint8_t F2HZ   : 1;   /*!< [5..5] 2Hz Flag                                                           */
            __IM uint8_t F1HZ   : 1;   /*!< [6..6] 1Hz Flag                                                           */
            __IM uint8_t R64OVF : 1;   /*!< [7..7] This bit indicates the overflow of F1HZ only when using
                                        *   time error adjustment function inlow-consumption clock
                                        *   mode.                                                                     */
        } R64CNT_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        union
        {
            __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */

            struct
            {
                __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
                                          *   counter b7 to b0.                                                         */
            } BCNT0_b;
        };

        union
        {
            __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */

            struct
            {
                __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
                                          *   a carry is generated, 1 is added to the tens place.                       */
                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
                uint8_t             : 1;
            } RSECCNT_b;
        };
    };
    __IM uint8_t RESERVED1;

    union
    {
        union
        {
            __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */

            struct
            {
                __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
                                          *   counter b15 to b8.                                                        */
            } BCNT1_b;
        };

        union
        {
            __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */

            struct
            {
                __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
                                          *   a carry is generated, 1 is added to the tens place.                       */
                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
                uint8_t             : 1;
            } RMINCNT_b;
        };
    };
    __IM uint8_t RESERVED2;

    union
    {
        union
        {
            __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */

            struct
            {
                __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
                                          *   counter b23 to b16.                                                       */
            } BCNT2_b;
        };

        union
        {
            __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */

            struct
            {
                __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
                                         *   carry is generated, 1 is added to the tens place.                         */
                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
                                         *   the ones place.                                                           */
                __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
                uint8_t          : 1;
            } RHRCNT_b;
        };
    };
    __IM uint8_t RESERVED3;

    union
    {
        union
        {
            __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */

            struct
            {
                __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
                                          *   counter b31 to b24.                                                       */
            } BCNT3_b;
        };

        union
        {
            __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */

            struct
            {
                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
                uint8_t            : 5;
            } RWKCNT_b;
        };
    };
    __IM uint8_t RESERVED4;

    union
    {
        __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */

        struct
        {
            __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
                                        *   is generated, 1 is added to the tens place.                               */
            __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
                                        *   ones place.                                                               */
            uint8_t : 2;
        } RDAYCNT_b;
    };
    __IM uint8_t RESERVED5;

    union
    {
        __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */

        struct
        {
            __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
                                        *   a carry is generated, 1 is added to the tens place.                       */
            __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
                                        *   the ones place.                                                           */
            uint8_t : 3;
        } RMONCNT_b;
    };
    __IM uint8_t RESERVED6;

    union
    {
        __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */

        struct
        {
            __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
                                        *   carry is generated, 1 is added to the tens place.                         */
            __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
                                        *   ones place. When a carry is generated in the tens place,
                                        *   1 is added to the hundreds place.                                         */
            uint16_t : 8;
        } RYRCNT_b;
    };

    union
    {
        union
        {
            __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */

            struct
            {
                __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
                                            *   corresponding to 32-bit binary counter b7 to b0.                          */
            } BCNT0AR_b;
        };

        union
        {
            __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */

            struct
            {
                __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
                __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
            } RSECAR_b;
        };
    };
    __IM uint8_t RESERVED7;

    union
    {
        union
        {
            __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */

            struct
            {
                __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
                                            *   corresponding to 32-bit binary counter b15 to b8.                         */
            } BCNT1AR_b;
        };

        union
        {
            __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */

            struct
            {
                __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
                __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
            } RMINAR_b;
        };
    };
    __IM uint8_t RESERVED8;

    union
    {
        union
        {
            __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */

            struct
            {
                __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
                                            *   counter b23 to b16.                                                       */
            } BCNT2AR_b;
        };

        union
        {
            __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */

            struct
            {
                __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
                __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
                __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
            } RHRAR_b;
        };
    };
    __IM uint8_t RESERVED9;

    union
    {
        union
        {
            __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */

            struct
            {
                __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
                                            *   counter b31 to b24.                                                       */
            } BCNT3AR_b;
        };

        union
        {
            __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */

            struct
            {
                __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
                uint8_t            : 4;
                __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
            } RWKAR_b;
        };
    };
    __IM uint8_t RESERVED10;

    union
    {
        union
        {
            __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */

            struct
            {
                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
                                        *   for setting the alarm enable corresponding to 32-bit binary
                                        *   counter b7 to b0.                                                         */
            } BCNT0AER_b;
        };

        union
        {
            __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */

            struct
            {
                __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
                __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
                uint8_t              : 1;
                __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
            } RDAYAR_b;
        };
    };
    __IM uint8_t RESERVED11;

    union
    {
        union
        {
            __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */

            struct
            {
                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
                                        *   for setting the alarm enable corresponding to 32-bit binary
                                        *   counter b15 to b8.                                                        */
            } BCNT1AER_b;
        };

        union
        {
            __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */

            struct
            {
                __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
                __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
                uint8_t             : 2;
                __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
            } RMONAR_b;
        };
    };
    __IM uint8_t RESERVED12;

    union
    {
        union
        {
            __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */

            struct
            {
                __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
                                         *   for setting the alarm enable corresponding to 32-bit binary
                                         *   counter b23 to b16.                                                       */
                uint16_t : 8;
            } BCNT2AER_b;
        };

        union
        {
            __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */

            struct
            {
                __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
                __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
                uint16_t            : 8;
            } RYRAR_b;
        };
    };

    union
    {
        union
        {
            __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */

            struct
            {
                __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
                                        *   for setting the alarm enable corresponding to 32-bit binary
                                        *   counter b31 to b24.                                                       */
            } BCNT3AER_b;
        };

        union
        {
            __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */

            struct
            {
                uint8_t           : 7;
                __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
            } RYRAREN_b;
        };
    };
    __IM uint8_t  RESERVED13;
    __IM uint16_t RESERVED14;

    union
    {
        __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */

        struct
        {
            __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
            __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
            __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
            __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
            __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
        } RCR1_b;
    };
    __IM uint8_t RESERVED15;

    union
    {
        __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */

        struct
        {
            __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
            __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
            __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
            __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
            __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
                                        *   the setting of this bit is disabled.)                                     */
            __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
                                        *   is selected, the setting of this bit is disabled.)                        */
            __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
            __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
        } RCR2_b;
    };
    __IM uint8_t  RESERVED16;
    __IM uint16_t RESERVED17;

    union
    {
        __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */

        struct
        {
            __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
            uint8_t              : 6;
            __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
        } RCR4_b;
    };
    __IM uint8_t RESERVED18;

    union
    {
        __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */

        struct
        {
            __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
                                        *   clock from the LOCOclock, this bit sets the comparison
                                        *   value of the 128-Hz clock cycle.                                          */
            uint16_t : 15;
        } RFRH_b;
    };

    union
    {
        __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */

        struct
        {
            __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
                                        *   clock from the main clock, this bit sets the comparison
                                        *   value of the 128-Hz clock cycle.                                          */
        } RFRL_b;
    };

    union
    {
        __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */

        struct
        {
            __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
                                        *   from the prescaler.                                                       */
            __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
        } RADJ_b;
    };
    __IM uint8_t RESERVED19;

    union
    {
        __IOM uint16_t RADJ2;          /*!< (@ 0x00000030) Time Error Adjustment Register 2                           */

        struct
        {
            uint16_t            : 5;
            __IOM uint16_t FADJ : 11;  /*!< [15..5] Fractional Adjust Value                                           */
        } RADJ2_b;
    };
    __IM uint16_t          RESERVED20[7];
    __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
    __IM uint16_t          RESERVED21[5];
    __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
} R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */

/* =========================================================================================================================== */
/* ================                                          R_SCI0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Serial Communications Interface (R_SCI0)
 */

typedef struct                         /*!< (@ 0x40118000) R_SCI0 Structure                                           */
{
    union
    {
        union
        {
            __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */

            struct
            {
                __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
                __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
                __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
                __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
                __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
                __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
                __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
            } SMR_b;
        };

        union
        {
            __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */

            struct
            {
                __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
                __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
                __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
                __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
                __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
                __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
            } SMR_SMCI_b;
        };
    };

    union
    {
        __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */

        struct
        {
            __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
        } BRR_b;
    };

    union
    {
        union
        {
            __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */

            struct
            {
                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
                                         *   mode when SMR.MP = 1)                                                     */
                __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
                __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
                __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
                __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
            } SCR_b;
        };

        union
        {
            __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */

            struct
            {
                __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
                __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
                __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
                __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
                __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
                __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
                __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
            } SCR_SMCI_b;
        };
    };

    union
    {
        __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */

        struct
        {
            __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
        } TDR_b;
    };

    union
    {
        union
        {
            __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */

            struct
            {
                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
                __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
            } SSR_b;
        };

        union
        {
            __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */

            struct
            {
                __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
                                         *   multi-processor) and FIFO selected)                                       */
                uint8_t            : 1;
                __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
                __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
                __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
            } SSR_FIFO_b;
        };

        union
        {
            __IOM uint8_t SSR_MANC;     /*!< (@ 0x00000004) Serial Status Register for Manchester Mode (SCMR.SMIF
                                         *                  = 0, and MMR.MANEN = 1)                                    */

            struct
            {
                __IOM uint8_t MER  : 1; /*!< [0..0] Manchester Error Flag Valid for Manchester mode only               */
                __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
                __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
            } SSR_MANC_b;
        };

        union
        {
            __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */

            struct
            {
                __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
                                         *   card interface mode.                                                      */
                __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
                                         *   mode.                                                                     */
                __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
                __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
                __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
                __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
                __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
                __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
            } SSR_SMCI_b;
        };
    };

    union
    {
        __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */

        struct
        {
            __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
        } RDR_b;
    };

    union
    {
        __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */

        struct
        {
            __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
            uint8_t            : 1;
            __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
                                        *   operation is to be in simple I2C mode.                                    */
            __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
                                        *   setting is invalid and a fixed data length of 8 bits is
                                        *   used in modes other than asynchronous mode.Set this bit
                                        *   to 1 if operation is to be in simple I2C mode.                            */
            __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
            uint8_t            : 2;
            __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
                                        *   in combination with the SMR.BCP[1:0] bits                                 */
        } SCMR_b;
    };

    union
    {
        __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */

        struct
        {
            __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
                                        *   asynchronous mode).                                                       */
            __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
                                        *   mode).                                                                    */
            __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
            __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
                                        *   only in asynchronous mode and SCR.CKE[1]=0)                               */
            __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
                                        *   mode)                                                                     */
            __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
                                        *   be 0 without simple I2C mode and asynchronous mode.)In
                                        *   asynchronous mode, for RXDn input only. In simple I2C mode,
                                        *   for RXDn/TxDn input.                                                      */
            __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
                                        *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
            __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
                                        *   in asynchronous mode)                                                     */
        } SEMR_b;
    };

    union
    {
        __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */

        struct
        {
            __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
            uint8_t            : 5;
        } SNFR_b;
    };

    union
    {
        __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */

        struct
        {
            __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
            uint8_t             : 2;
            __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
                                        *   signal from the on-chip baud rate generator.                              */
        } SIMR1_b;
    };

    union
    {
        __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */

        struct
        {
            __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
            __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
            uint8_t               : 3;
            __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
            uint8_t               : 2;
        } SIMR2_b;
    };

    union
    {
        __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */

        struct
        {
            __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
            __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
            __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
            __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
                                           *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
            __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
            __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
        } SIMR3_b;
    };

    union
    {
        __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */

        struct
        {
            __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
            uint8_t              : 7;
        } SISR_b;
    };

    union
    {
        __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */

        struct
        {
            __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
            __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
            __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
            __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
            __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
            uint8_t              : 1;
            __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
            __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
        } SPMR_b;
    };

    union
    {
        union
        {
            __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */

            struct
            {
                __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
            } TDRHL_b;
        };

        union
        {
            __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */

            struct
            {
                __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
                __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
                                         *   mode and SMR.MP=1 and FIFO selected)                                      */
                uint16_t : 6;
            } FTDRHL_b;
        };

        union
        {
            __IOM uint16_t TDRHL_MAN;     /*!< (@ 0x0000000E) Transmit Data Register for Manchester Mode (MMR.MANEN
                                           *                  = 1)                                                       */

            struct
            {
                __IOM uint16_t TDAT  : 9; /*!< [8..0] Serial transmit data                                               */
                __IOM uint16_t MPBT  : 1; /*!< [9..9] Multi-processor Transfer Bit Flag                                  */
                uint16_t             : 2;
                __IOM uint16_t TSYNC : 1; /*!< [12..12] Transmit SYNC data bit                                           */
                uint16_t             : 3;
            } TDRHL_MAN_b;
        };

        struct
        {
            union
            {
                __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */

                struct
                {
                    __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
                                             *   mode(including multi-processor) or clock synchronous mode,
                                             *   and FIFO selected)                                                        */
                    __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
                                             *   mode and SMR.MP=1 and FIFO selected)                                      */
                    uint8_t : 6;
                } FTDRH_b;
            };

            union
            {
                __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */

                struct
                {
                    __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
                                             *   mode(including multi-processor) or clock synchronous mode,
                                             *   and FIFO selected)                                                        */
                } FTDRL_b;
            };
        };
    };

    union
    {
        union
        {
            __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */

            struct
            {
                __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
            } RDRHL_b;
        };

        union
        {
            __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */

            struct
            {
                __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
                __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
                                         *   with SMR.MP=1 and FIFO selected) It can read multi-processor
                                         *   bit corresponded to serial receive data(RDATA[8:0])                       */
                __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
                __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
                __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
                __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
                __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
                uint16_t           : 1;
            } FRDRHL_b;
        };

        union
        {
            __IM uint16_t RDRHL_MAN;     /*!< (@ 0x00000010) Receive Data Register for Manchester Mode (MMR.MANEN
                                          *                  = 1)                                                       */

            struct
            {
                __IM uint16_t RDAT  : 9; /*!< [8..0] Serial Receive Data                                                */
                __IM uint16_t MPB   : 1; /*!< [9..9] Multi-processor Bit                                                */
                uint16_t            : 2;
                __IM uint16_t RSYNC : 1; /*!< [12..12] Receive SYNC data bit                                            */
                uint16_t            : 3;
            } RDRHL_MAN_b;
        };

        struct
        {
            union
            {
                __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */

                struct
                {
                    __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
                                             *   multi-processor) or clock synchronous mode, and FIFO selected)            */
                    __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
                                             *   with SMR.MP=1 and FIFO selected) It can read multi-processor
                                             *   bit corresponded to serial receive data(RDATA[8:0])                       */
                    __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
                    __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
                    __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
                    __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
                    __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
                    uint8_t           : 1;
                } FRDRH_b;
            };

            union
            {
                __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */

                struct
                {
                    __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
                                             *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
                                             *   When reading both of FRDRH register and FRDRL register,
                                             *   please read by an order of the FRDRH register and the FRDRL
                                             *   register.                                                                 */
                } FRDRL_b;
            };
        };
    };

    union
    {
        __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */

        struct
        {
            __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
        } MDDR_b;
    };

    union
    {
        __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */

        struct
        {
            __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
            uint8_t             : 2;
            __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
            __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
            uint8_t             : 1;
            __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
                                        *   multi-processor)                                                          */
            __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
                                        *   mode(including multi-processor)                                           */
        } DCCR_b;
    };

    union
    {
        __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */

        struct
        {
            __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
                                        *   multi-processor) or clock synchronous mode)                               */
            __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
            __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
            __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
                                        *   reception data ready, the interrupt request is selected.)                 */
            __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
                                        *   mode(including multi-processor) or clock synchronous mode)                */
            __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
                                        *   mode(including multi-processor) or clock synchronous mode)                */
            __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
                                        *   in asynchronous mode(including multi-processor) or clock
                                        *   synchronous mode)                                                         */
        } FCR_b;
    };

    union
    {
        __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */

        struct
        {
            __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
                                        *   data stored in FRDRH and FRDRL(Valid only in asynchronous
                                        *   mode(including multi-processor) or clock synchronous mode,
                                        *   while FCR.FM=1)                                                           */
            uint16_t        : 3;
            __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
                                        *   data stored in FTDRH and FTDRL(Valid only in asynchronous
                                        *   mode(including multi-processor) or clock synchronous mode,
                                        *   while FCR.FM=1)                                                           */
            uint16_t : 3;
        } FDR_b;
    };

    union
    {
        __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */

        struct
        {
            __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
                                        *   multi-processor) or clock synchronous mode, and FIFO selected)            */
            uint16_t           : 1;
            __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
                                        *   a framing error among the receive data stored in the receive
                                        *   FIFO data register (FRDRH and FRDRL).                                     */
            uint16_t           : 1;
            __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
                                        *   a parity error among the receive data stored in the receive
                                        *   FIFO data register (FRDRH and FRDRL).                                     */
            uint16_t : 3;
        } LSR_b;
    };

    union
    {
        __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */

        struct
        {
            __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
                                        *   wake-up function                                                          */
            uint16_t : 7;
        } CDR_b;
    };

    union
    {
        __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */

        struct
        {
            __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
                                        *   is shown.)                                                                */
            __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
                                        *   TxD terminal is selected when SCR.TE = 0.)                                */
            __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
                                        *   of SPB2DT is output to TxD terminal.)                                     */
            uint8_t            : 1;
            __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
            __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
            __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
            __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
        } SPTR_b;
    };

    union
    {
        __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */

        struct
        {
            __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
            __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
            __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
            __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
        } ACTR_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        union
        {
            __IOM uint8_t ESMER;        /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */

            struct
            {
                __IOM uint8_t ESME : 1; /*!< [0..0] Extended Serial Mode Enable                                        */
                uint8_t            : 7;
            } ESMER_b;
        };

        union
        {
            __IOM uint8_t MMR;            /*!< (@ 0x00000020) Manchester Mode Register                                   */

            struct
            {
                __IOM uint8_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
                __IOM uint8_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
                __IOM uint8_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
                uint8_t              : 1;
                __IOM uint8_t SYNVAL : 1; /*!< [4..4] SYNC Value Setting                                                 */
                __IOM uint8_t SYNSEL : 1; /*!< [5..5] SYNC Select                                                        */
                __IOM uint8_t SBSEL  : 1; /*!< [6..6] Start Bit Select                                                   */
                __IOM uint8_t MANEN  : 1; /*!< [7..7] Manchester Mode Enable                                             */
            } MMR_b;
        };
    };

    union
    {
        __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */

        struct
        {
            uint8_t             : 1;
            __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
            __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
            __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
            uint8_t             : 4;
        } CR0_b;
    };

    union
    {
        union
        {
            __IOM uint8_t CR1;           /*!< (@ 0x00000022) Control Register 1                                         */

            struct
            {
                __IOM uint8_t BFE   : 1; /*!< [0..0] Break Field Enable                                                 */
                __IOM uint8_t CF0RE : 1; /*!< [1..1] Control Field 0 Reception Enable                                   */
                __IOM uint8_t CF1DS : 2; /*!< [3..2] Control Field 1 Data Register Select                               */
                __IOM uint8_t PIBE  : 1; /*!< [4..4] Priority Interrupt Bit Enable                                      */
                __IOM uint8_t PIBS  : 3; /*!< [7..5] Priority Interrupt Bit Select                                      */
            } CR1_b;
        };

        union
        {
            __IOM uint8_t TMPR;          /*!< (@ 0x00000022) Transmit Manchester Preface Setting Register               */

            struct
            {
                __IOM uint8_t TPLEN : 4; /*!< [3..0] Transmit Preface Length                                            */
                __IOM uint8_t TPPAT : 2; /*!< [5..4] Transmit Preface Pattern                                           */
                uint8_t             : 2;
            } TMPR_b;
        };
    };

    union
    {
        union
        {
            __IOM uint8_t CR2;          /*!< (@ 0x00000023) Control Register 2                                         */

            struct
            {
                __IOM uint8_t DFCS : 3; /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
                uint8_t            : 1;
                __IOM uint8_t BCCS : 2; /*!< [5..4] Bus Collision Detection Clock Select                               */
                __IOM uint8_t RTS  : 2; /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
            } CR2_b;
        };

        union
        {
            __IOM uint8_t RMPR;          /*!< (@ 0x00000023) Receive Manchester Preface Setting Register                */

            struct
            {
                __IOM uint8_t RPLEN : 4; /*!< [3..0] Receive Preface Length                                             */
                __IOM uint8_t RPPAT : 2; /*!< [5..4] Receive Preface Pattern                                            */
                uint8_t             : 2;
            } RMPR_b;
        };
    };

    union
    {
        union
        {
            __IOM uint8_t CR3;          /*!< (@ 0x00000024) Control Register 3                                         */

            struct
            {
                __IOM uint8_t SDST : 1; /*!< [0..0] Start Frame Detection Start                                        */
                uint8_t            : 7;
            } CR3_b;
        };

        union
        {
            __IOM uint8_t MESR;         /*!< (@ 0x00000024) Manchester Extended Error Status Register                  */

            struct
            {
                __IOM uint8_t PFER : 1; /*!< [0..0] Preface Error Flag                                                 */
                __IOM uint8_t SYER : 1; /*!< [1..1] SYNC Error Flag                                                    */
                __IOM uint8_t SBER : 1; /*!< [2..2] Start Bit Error Flag                                               */
                uint8_t            : 5;
            } MESR_b;
        };
    };

    union
    {
        union
        {
            __IOM uint8_t PCR;            /*!< (@ 0x00000025) Port Control Register                                      */

            struct
            {
                __IOM uint8_t TXDXPS : 1; /*!< [0..0] TXDXn Signal Polarity Select                                       */
                __IOM uint8_t RXDXPS : 1; /*!< [1..1] RXDXn Signal Polarity Select                                       */
                uint8_t              : 2;
                __IOM uint8_t SHARPS : 1; /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
                uint8_t              : 3;
            } PCR_b;
        };

        union
        {
            __IOM uint8_t MECR;           /*!< (@ 0x00000025) Manchester Extended Error Control Register                 */

            struct
            {
                __IOM uint8_t PFEREN : 1; /*!< [0..0] Preface Error Flag                                                 */
                __IOM uint8_t SYEREN : 1; /*!< [1..1] Receive SYNC Error Enable                                          */
                __IOM uint8_t SBEREN : 1; /*!< [2..2] Start Bit Error Enable                                             */
                uint8_t              : 5;
            } MECR_b;
        };
    };

    union
    {
        __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */

        struct
        {
            __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
            __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
            __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
            __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
            __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
            __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
            uint8_t              : 2;
        } ICR_b;
    };

    union
    {
        __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */

        struct
        {
            __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
            __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
            __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
            __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
            __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
            __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
            uint8_t            : 2;
        } STR_b;
    };

    union
    {
        __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */

        struct
        {
            __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
            __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
            __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
            __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
            __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
            __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
            uint8_t              : 2;
        } STCR_b;
    };
    __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */

    union
    {
        __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */

        struct
        {
            __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
            __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
        } CF0CR_b;
    };
    __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
    __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
    __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */

    union
    {
        __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */

        struct
        {
            __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
            __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
            __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
            __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
            __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
            __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
            __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
            __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
        } CF1CR_b;
    };
    __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */

    union
    {
        __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */

        struct
        {
            __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
            uint8_t            : 7;
        } TCR_b;
    };

    union
    {
        __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */

        struct
        {
            __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
            uint8_t            : 1;
            __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
            __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
            uint8_t            : 1;
        } TMR_b;
    };
    __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
    __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
    __IM uint16_t RESERVED1[4];

    union
    {
        __IOM uint8_t SCIMSKEN;        /*!< (@ 0x0000003C) SCI5 TXD Output Mask Enable Register                       */

        struct
        {
            __IOM uint8_t MSKEN : 1;   /*!< [0..0] SCI5 TXD Output Mask Enable                                        */
            uint8_t             : 7;
        } SCIMSKEN_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;
} R_SCI0_Type;                         /*!< Size = 64 (0x40)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_SLCDC                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Segment LCD Controller/Driver (R_SLCDC)
 */

typedef struct                         /*!< (@ 0x400D4000) R_SLCDC Structure                                          */
{
    union
    {
        __IOM uint8_t LCDM0;           /*!< (@ 0x00000000) LCD Mode Register 0                                        */

        struct
        {
            __IOM uint8_t LBAS  : 2;   /*!< [1..0] LCD Display Bias Method Select                                     */
            __IOM uint8_t LDTY  : 3;   /*!< [4..2] Time Slice of LCD Display Select                                   */
            __IOM uint8_t LWAVE : 1;   /*!< [5..5] LCD display waveform selection                                     */
            __IOM uint8_t MDSET : 2;   /*!< [7..6] LCD drive voltage generator selection                              */
        } LCDM0_b;
    };

    union
    {
        __IOM uint8_t LCDM1;           /*!< (@ 0x00000001) LCD Mode Register 1                                        */

        struct
        {
            __IOM uint8_t LCDVLM : 1;  /*!< [0..0] Voltage Boosting Pin Initial Value Switching Control               */
            uint8_t              : 2;
            __IOM uint8_t LCDSEL : 1;  /*!< [3..3] Display data area control                                          */
            __IOM uint8_t BLON   : 1;  /*!< [4..4] Display data area control                                          */
            __IOM uint8_t VLCON  : 1;  /*!< [5..5] Voltage boost circuit or capacitor split circuit operation
                                        *   enable/disable                                                            */
            __IOM uint8_t SCOC  : 1;   /*!< [6..6] LCD Display Enable/Disable                                         */
            __IOM uint8_t LCDON : 1;   /*!< [7..7] LCD Display Enable/Disable                                         */
        } LCDM1_b;
    };

    union
    {
        __IOM uint8_t LCDC0;           /*!< (@ 0x00000002) LCD Clock Control Register 0                               */

        struct
        {
            __IOM uint8_t LCDC : 6;    /*!< [5..0] LCD clock (LCDCL)                                                  */
            uint8_t            : 2;
        } LCDC0_b;
    };

    union
    {
        __IOM uint8_t VLCD;            /*!< (@ 0x00000003) LCD Boost Level Control Register                           */

        struct
        {
            __IOM uint8_t VLCD   : 5;  /*!< [4..0] Reference Voltage(Contrast Adjustment) Select                      */
            uint8_t              : 2;
            __IOM uint8_t MDSET2 : 1;  /*!< [7..7] Reference Voltage Selection                                        */
        } VLCD_b;
    };
    __IM uint8_t RESERVED[252];

    union
    {
        __IOM uint8_t SEG[64];         /*!< (@ 0x00000100) LCD Display Data Array                                     */

        struct
        {
            __IOM uint8_t A : 4;       /*!< [3..0] A-Pattern Area                                                     */
            __IOM uint8_t B : 4;       /*!< [7..4] B-Pattern Area                                                     */
        } SEG_b[64];
    };
} R_SLCDC_Type;                        /*!< Size = 320 (0x140)                                                        */

/* =========================================================================================================================== */
/* ================                                          R_SPI0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Serial Peripheral Interface (R_SPI0)
 */

typedef struct                         /*!< (@ 0x4011A000) R_SPI0 Structure                                           */
{
    union
    {
        __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */

        struct
        {
            __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
            __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
            __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
            __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
            __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
            __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
            __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
            __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
        } SPCR_b;
    };

    union
    {
        __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */

        struct
        {
            __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
            __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
            __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
            __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
            __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
            __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
            __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
            __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
        } SSLP_b;
    };

    union
    {
        __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */

        struct
        {
            __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
            __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
            uint8_t             : 2;
            __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
            __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
            uint8_t             : 2;
        } SPPCR_b;
    };

    union
    {
        __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */

        struct
        {
            __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
            __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
            __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
            __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
            __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
            __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
            __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
            __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
        } SPSR_b;
    };

    union
    {
        __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
        __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
        __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
    };

    union
    {
        __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */

        struct
        {
            __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
                                        *   the SPCMD0 to SPCMD07 registers are to be referenced is
                                        *   changed in accordance with the sequence length that is
                                        *   set in these bits. The relationship among the setting of
                                        *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
                                        *   referenced by the RSPI is shown above. However, the RSPI
                                        *   in slave mode always references SPCMD0.                                   */
            uint8_t : 5;
        } SPSCR_b;
    };

    union
    {
        __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */

        struct
        {
            __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
            uint8_t            : 1;
            __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
            uint8_t            : 1;
        } SPSSR_b;
    };

    union
    {
        __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */

        struct
        {
            __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
        } SPBR_b;
    };

    union
    {
        __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */

        struct
        {
            __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
            __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
            __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
            __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
            __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
            uint8_t              : 1;
        } SPDCR_b;
    };

    union
    {
        __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */

        struct
        {
            __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
            uint8_t             : 5;
        } SPCKD_b;
    };

    union
    {
        __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */

        struct
        {
            __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
            uint8_t             : 5;
        } SSLND_b;
    };

    union
    {
        __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */

        struct
        {
            __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
            uint8_t             : 5;
        } SPND_b;
    };

    union
    {
        __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */

        struct
        {
            __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
            __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
            __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
            __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
            __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
            __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
        } SPCR2_b;
    };

    union
    {
        __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */

        struct
        {
            __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
            __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
            __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
            __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
            __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
            __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
            __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
            __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
            __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
            __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
        } SPCMD_b[8];
    };

    union
    {
        __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */

        struct
        {
            __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
            __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
            uint8_t            : 6;
        } SPDCR2_b;
    };

    union
    {
        __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */

        struct
        {
            __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
            __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
            uint8_t              : 2;
            __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
            uint8_t              : 3;
        } SPCR3_b;
    };
    __IM uint16_t RESERVED;
    __IM uint32_t RESERVED1[6];
    __IM uint16_t RESERVED2;

    union
    {
        __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */

        struct
        {
            uint16_t              : 4;
            __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
            uint16_t              : 3;
            __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
            uint16_t              : 1;
            __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
        } SPPR_b;
    };
} R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_SRAM                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief SRAM (R_SRAM)
 */

typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
{
    union
    {
        __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */

        struct
        {
            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
            uint8_t           : 7;
        } PARIOAD_b;
    };
    __IM uint8_t RESERVED[3];

    union
    {
        __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */

        struct
        {
            __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
            __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
        } SRAMPRCR_b;
    };
    __IM uint8_t  RESERVED1[3];
    __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
    __IM uint8_t  RESERVED2[3];

    union
    {
        __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */

        struct
        {
            __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
            __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
        } SRAMPRCR2_b;
    };
    __IM uint8_t RESERVED3[179];

    union
    {
        __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */

        struct
        {
            __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
            uint8_t              : 6;
        } ECCMODE_b;
    };

    union
    {
        __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */

        struct
        {
            __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
            uint8_t               : 7;
        } ECC2STS_b;
    };

    union
    {
        __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */

        struct
        {
            __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
            uint8_t               : 7;
        } ECC1STSEN_b;
    };

    union
    {
        __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */

        struct
        {
            __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
            uint8_t               : 7;
        } ECC1STS_b;
    };

    union
    {
        __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */

        struct
        {
            __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
            __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
        } ECCPRCR_b;
    };
    __IM uint8_t RESERVED4[11];

    union
    {
        __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */

        struct
        {
            __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
            __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
        } ECCPRCR2_b;
    };
    __IM uint8_t RESERVED5[3];

    union
    {
        __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */

        struct
        {
            __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
            uint8_t              : 7;
        } ECCETST_b;
    };
    __IM uint8_t RESERVED6[3];

    union
    {
        __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */

        struct
        {
            __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
            uint8_t           : 7;
        } ECCOAD_b;
    };
} R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */

/* =========================================================================================================================== */
/* ================                                          R_SSI0                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
 */

typedef struct                         /*!< (@ 0x4009D000) R_SSI0 Structure                                           */
{
    union
    {
        __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */

        struct
        {
            __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
            __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
            uint32_t            : 1;
            __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
                                        *   of outputting serial data is rewritten to 0 but data transmission
                                        *   is not stopped. Write dummy data to the SSIFTDR not to
                                        *   generate a transmit underflow because the number of data
                                        *   in the transmit FIFO is decreasing.                                       */
            __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
            __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
            __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
            __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
            __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
            __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
            __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
            __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
                                        *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
                                        *   are prohibited.                                                           */
            uint32_t           : 1;
            __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
                                        *   bit clock frequency/2 fs.                                                 */
            __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
            __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
            uint32_t             : 1;
            __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
            __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
            __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
            __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
            __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
            __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
            uint32_t             : 1;
        } SSICR_b;
    };

    union
    {
        __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */

        struct
        {
            __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
            __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
            __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
            __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
            __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
            uint32_t             : 18;
            __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
            __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
                                        *   Writable only to clear the flag. Confirm the value is 1
                                        *   and then write 0.                                                         */
            __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
                                        *   Writable only to clear the flag. Confirm the value is 1
                                        *   and then write 0.                                                         */
            __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
                                        *   Writable only to clear the flag. Confirm the value is 1
                                        *   and then write 0.                                                         */
            __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
                                        *   Writable only to clear the flag. Confirm the value is 1
                                        *   and then write 0.                                                         */
            uint32_t : 2;
        } SSISR_b;
    };
    __IM uint32_t RESERVED[2];

    union
    {
        __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */

        struct
        {
            __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
            __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
            __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
                                        *   clearing either the RDF flag (see the description of the
                                        *   RDF bit for details) or RIE bit.                                          */
            __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
                                        *   clearing either the TDE flag (see the description of the
                                        *   TDE bit for details) or TIE bit.                                          */
            __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
            __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
                                        *   are the number of empty stages in SSIFTDR at which the
                                        *   TDE flag is set.                                                          */
            uint32_t              : 3;
            __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
            uint32_t              : 4;
            __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
            uint32_t              : 14;
            __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
        } SSIFCR_b;
    };

    union
    {
        __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */

        struct
        {
            __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
                                        *   is a 32-byte FIFO register, the maximum number of data
                                        *   bytes that can be read from it while the RDF flag is 1
                                        *   is indicated in the RDC[3:0] flags. If reading data from
                                        *   the SSIFRDR register is continued after all the data is
                                        *   read, undefined values will be read.                                      */
            uint32_t          : 7;
            __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
                                        *   units stored in SSIFRDR)                                                  */
            uint32_t           : 2;
            __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
                                        *   is a 32-byte FIFO register, the maximum number of bytes
                                        *   that can be written to it while the TDE flag is 1 is 8
                                        *   - TDC[3:0]. If writing data to the SSIFTDR register is
                                        *   continued after all the data is written, writing will be
                                        *   invalid and an overflow occurs.                                           */
            uint32_t          : 7;
            __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
                                        *   data units stored in SSIFTDR)                                             */
            uint32_t : 2;
        } SSIFSR_b;
    };

    union
    {
        union
        {
            __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */

            struct
            {
                __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
                                             *   eight stages of 32-bit registers for storing data to be
                                             *   serially transmitted. NOTE: that when the SSIFTDR register
                                             *   is full of data (32 bytes), the next data cannot be written
                                             *   to it. If writing is attempted, it will be ignored and
                                             *   an overflow occurs.                                                       */
            } SSIFTDR_b;
        };
        __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
        __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
    };

    union
    {
        union
        {
            __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */

            struct
            {
                __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
                                             *   stages of 32-bit registers for storing serially received
                                             *   data.                                                                     */
            } SSIFRDR_b;
        };
        __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
        __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
    };

    union
    {
        __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */

        struct
        {
            __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
            uint32_t               : 6;
            __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
            __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
                                         *   Idle Status                                                               */
            uint32_t : 22;
        } SSIOFR_b;
    };

    union
    {
        __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */

        struct
        {
            __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
            uint32_t            : 3;
            __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
            uint32_t            : 19;
        } SSISCR_b;
    };
} R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */

/* =========================================================================================================================== */
/* ================                                         R_SYSTEM                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief System Pins (R_SYSTEM)
 */

typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
{
    __IM uint32_t RESERVED[3];

    union
    {
        __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */

        struct
        {
            uint16_t            : 15;
            __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
        } SBYCR_b;
    };
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2[4];

    union
    {
        __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */

        struct
        {
            __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
            uint32_t            : 1;
            __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
            uint32_t            : 1;
            __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
            uint32_t            : 1;
            __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
            uint32_t            : 1;
            __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
            uint32_t            : 5;
            __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
            uint32_t            : 1;
            __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
            uint32_t            : 1;
        } SCKDIVCR_b;
    };
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */

        struct
        {
            __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
            uint8_t             : 5;
        } SCKSCR_b;
    };
    __IM uint8_t RESERVED4;

    union
    {
        __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */

        struct
        {
            __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
            uint16_t                : 2;
            __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
            uint16_t                : 3;
            __IOM uint16_t PLLMUL   : 5; /*!< [12..8] PLL Frequency Multiplication Factor Select [PLL Frequency
                                          *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
                                          *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
                                          *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
                                          *   111011: x30.0                                                             */
            uint16_t : 3;
        } PLLCCR_b;
    };

    union
    {
        __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */

        struct
        {
            __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
            uint8_t              : 7;
        } PLLCR_b;
    };
    __IM uint8_t  RESERVED5;
    __IM uint32_t RESERVED6;
    __IM uint8_t  RESERVED7;

    union
    {
        __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */

        struct
        {
            __IOM uint8_t MEMWAIT : 2; /*!< [1..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
                                        *   is prohibited when SCKDIVCR.ICK selects division by 1 and
                                        *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
                                        *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
            uint8_t : 6;
        } MEMWAIT_b;
    };

    union
    {
        __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */

        struct
        {
            __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
            uint8_t             : 7;
        } MOSCCR_b;
    };
    __IM uint8_t  RESERVED8;
    __IM uint16_t RESERVED9;

    union
    {
        __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */

        struct
        {
            __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
            uint8_t             : 7;
        } HOCOCR_b;
    };
    __IM uint8_t RESERVED10;

    union
    {
        __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */

        struct
        {
            __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
            uint8_t             : 7;
        } MOCOCR_b;
    };
    __IM uint8_t  RESERVED11;
    __IM uint16_t RESERVED12;

    union
    {
        __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */

        struct
        {
            __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
                                        *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
                                        *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
            uint8_t               : 2;
            __IM uint8_t MOSCSF   : 1; /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
            uint8_t               : 1;
            __IM uint8_t PLLSF    : 1; /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
            uint8_t               : 1;
            __IM uint8_t PLLRTCSF : 1; /*!< [7..7] PLL_RTC Clock Oscillation Stabilization Flag                       */
        } OSCSF_b;
    };
    __IM uint8_t RESERVED13;

    union
    {
        __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */

        struct
        {
            __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
            uint8_t              : 1;
            __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
            __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
        } CKOCR_b;
    };
    __IM uint8_t RESERVED14;

    union
    {
        __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */

        struct
        {
            __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
            uint8_t              : 6;
            __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
        } OSTDCR_b;
    };

    union
    {
        __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */

        struct
        {
            __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
            uint8_t             : 7;
        } OSTDSR_b;
    };

    union
    {
        __IOM uint16_t SOSTDCR;           /*!< (@ 0x00000042) Sub-Clock Oscillation Stop Detection Control
                                           *                  Register                                                   */

        struct
        {
            __IOM uint16_t SOSDCCMP : 12; /*!< [11..0] Sub-Clock Oscillation Stop Detection Time                         */
            __IOM uint16_t SOSTDIE  : 1;  /*!< [12..12] Sub-Clock Oscillation Stop Detection Interrupt Enable            */
            __IM uint16_t  SOSTDF   : 1;  /*!< [13..13] Sub-Clock Oscillation Stop Detection Flag                        */
            __IM uint16_t  SOSDCF   : 1;  /*!< [14..14] Status of Sub-Clock Oscillation Stop Detector Operation          */
            __IOM uint16_t SOSDCE   : 1;  /*!< [15..15] Control of Sub-Clock Oscillation Stop Detector Operation         */
        } SOSTDCR_b;
    };
    __IM uint32_t RESERVED15;
    __IM uint16_t RESERVED16;

    union
    {
        __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */

        struct
        {
            __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
            uint8_t               : 7;
        } PLL2CR_b;
    };
    __IM uint8_t  RESERVED17;
    __IM uint32_t RESERVED18;

    union
    {
        __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */

        struct
        {
            __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
            uint8_t                 : 4;
            __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
        } SLCDSCKCR_b;
    };
    __IM uint8_t  RESERVED19;
    __IM uint16_t RESERVED20[2];

    union
    {
        __IOM uint8_t PLLRTCCR;          /*!< (@ 0x00000056) PLL_RTC Control Register                                   */

        struct
        {
            __IOM uint8_t PLLRTCSTP : 1; /*!< [0..0] PLL_RTC Stop Control                                               */
            uint8_t                 : 7;
        } PLLRTCCR_b;
    };
    __IM uint8_t  RESERVED21;
    __IM uint32_t RESERVED22[2];
    __IM uint8_t  RESERVED23;

    union
    {
        __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */

        struct
        {
            __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
                                         +126 0111_1111 : +127These bits are added to original MOCO
                                         *   trimming bits                                                             */
        } MOCOUTCR_b;
    };

    union
    {
        __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */

        struct
        {
            __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
                                         +126 0111_1111 : +127These bits are added to original HOCO
                                         *   trimming bits                                                             */
        } HOCOUTCR_b;
    };
    __IM uint8_t  RESERVED24;
    __IM uint32_t RESERVED25[2];
    __IM uint16_t RESERVED26;

    union
    {
        __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */

        struct
        {
            __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
            uint8_t                  : 5;
        } CANFDCKDIVCR_b;
    };
    __IM uint8_t RESERVED27[2];

    union
    {
        __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */

        struct
        {
            __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
            uint8_t                : 5;
        } I3CCKDIVCR_b;
    };
    __IM uint16_t RESERVED28;

    union
    {
        __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */

        struct
        {
            __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
            uint8_t                 : 3;
            __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
            __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
        } USBCKCR_b;
    };
    __IM uint8_t RESERVED29;

    union
    {
        __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */

        struct
        {
            __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
            uint8_t                   : 3;
            __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
            __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
        } CANFDCKCR_b;
    };
    __IM uint8_t RESERVED30[2];

    union
    {
        __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */

        struct
        {
            __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
            uint8_t                 : 3;
            __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
            __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
        } I3CCKCR_b;
    };
    __IM uint16_t RESERVED31;
    __IM uint32_t RESERVED32[5];
    __IM uint16_t RESERVED33;

    union
    {
        __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */

        struct
        {
            __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
                                         *   than in asynchronous mode.                                                */
            __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
            uint8_t                : 5;
            __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
        } SNZCR_b;
    };
    __IM uint8_t RESERVED34;

    union
    {
        __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */

        struct
        {
            __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
            __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
            __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
            __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
            __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
            uint8_t                 : 2;
            __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
                                          *   to 1 other than in asynchronous mode.                                     */
        } SNZEDCR_b;
    };

    union
    {
        __IOM uint8_t SNZEDCR1;        /*!< (@ 0x00000095) Snooze End Control Register 1                              */

        struct
        {
            uint8_t                 : 1;
            __IOM uint8_t CTSUNAJED : 1; /*!< [1..1] CTSU2SLa non-touch automatic judgment Snooze End Enable            */
            uint8_t                 : 6;
        } SNZEDCR1_b;
    };
    __IM uint16_t RESERVED35;

    union
    {
        __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */

        struct
        {
            __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
            __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
            __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
            __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
            __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
            __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
            __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
            __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
            __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
            __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
            __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
            __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
            __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
            __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
            __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
            __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
            uint32_t                  : 7;
            __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
                                            *   request                                                                   */
            __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
            __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
            uint32_t                  : 2;
            __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
                                            *   request                                                                   */
            __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
                                            *   snooze request                                                            */
            __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
                                            *   snooze request                                                            */
            uint32_t : 1;
        } SNZREQCR_b;
    };
    __IM uint16_t RESERVED36;
    __IM uint8_t  RESERVED37;

    union
    {
        __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */

        struct
        {
            __IOM uint8_t PSMC0 : 1;   /*!< [0..0] Power save memory control.                                         */
            __IOM uint8_t PSMC1 : 1;   /*!< [1..1] Power save memory control.                                         */
            __IOM uint8_t PSMC2 : 1;   /*!< [2..2] Power save memory control.                                         */
            __IOM uint8_t PSMC3 : 1;   /*!< [3..3] Power save memory control.                                         */
            __IOM uint8_t PSMC4 : 1;   /*!< [4..4] Power save memory control.                                         */
            __IOM uint8_t PSMC5 : 1;   /*!< [5..5] Power save memory control.                                         */
            uint8_t             : 2;
        } PSMCR_b;
    };

    union
    {
        __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */

        struct
        {
            __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
            uint8_t              : 2;
            __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
            uint8_t              : 3;
        } OPCCR_b;
    };
    __IM uint8_t RESERVED38;

    union
    {
        __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */

        struct
        {
            __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
            uint8_t            : 4;
        } MOSCWTCR_b;
    };
    __IM uint8_t  RESERVED39;
    __IM uint32_t RESERVED40;
    __IM uint16_t RESERVED41;

    union
    {
        __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */

        struct
        {
            __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
            uint8_t               : 3;
            __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
            uint8_t               : 3;
        } SOPCCR_b;
    };
    __IM uint8_t RESERVED42;

    union
    {
        __IOM uint8_t LDOCR;           /*!< (@ 0x000000AC) LDO control register                                       */

        struct
        {
            __IOM uint8_t CHG0 : 1;    /*!< [0..0] Charge up 0                                                        */
            uint8_t            : 7;
        } LDOCR_b;
    };
    __IM uint8_t  RESERVED43;
    __IM uint16_t RESERVED44;
    __IM uint32_t RESERVED45[4];

    union
    {
        __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */

        struct
        {
            __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
                                        *   only to clear the flag. Confirm the value is 1 and then
                                        *   write 0.                                                                  */
            __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
            __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
                                        *   the flag. Confirm the value is 1 and then write 0.                        */
            uint16_t             : 5;
            __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
                                        *   to clear the flag. Confirm the value is 1 and then write
                                        *   0.                                                                        */
            __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
                                        *   clear the flag. Confirm the value is 1 and then write 0.                  */
            uint16_t              : 1;
            __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
                                        *   to clear the flag. Confirm the value is 1 and then write
                                        *   0.                                                                        */
            uint16_t             : 1;
            __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
            uint16_t             : 1;
            __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
        } RSTSR1_b;
    };
    __IM uint16_t RESERVED46;
    __IM uint32_t RESERVED47[3];

    union
    {
        __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */

        struct
        {
            __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
                                          *   (UCLK).                                                                   */
            uint8_t : 7;
        } USBCKCR_ALT_b;
    };
    __IM uint8_t  RESERVED48;
    __IM uint16_t RESERVED49;
    __IM uint32_t RESERVED50[3];

    union
    {
        __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */

        struct
        {
            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
            uint8_t              : 5;
        } LVD1CR1_b;
    };

    union
    {
        __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */

        struct
        {
            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
                                        *   0 can be written to this bit. After writing 0 to this bit,
                                        *   it takes 2 system clock cycles for the bit to be read as
                                        *   0.                                                                        */
            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
            uint8_t          : 6;
        } LVD1SR_b;
    };

    union
    {
        __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */

        struct
        {
            __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
            __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
            uint8_t              : 5;
        } LVD2CR1_b;
    };

    union
    {
        __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */

        struct
        {
            __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
                                        *   0 can be written to this bit. After writing 0 to this bit,
                                        *   it takes 2 system clock cycles for the bit to be read as
                                        *   0.                                                                        */
            __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
            uint8_t          : 6;
        } LVD2SR_b;
    };
    __IM uint32_t RESERVED51[3];

    union
    {
        __IOM uint8_t SRMPSCR;         /*!< (@ 0x000000F0) SRAM Power State Control Register                          */

        struct
        {
            __IOM uint8_t SPSC0 : 1;   /*!< [0..0] SRAM Power State Control                                           */
            __IOM uint8_t SPSC1 : 1;   /*!< [1..1] SRAM Power State Control                                           */
            __IOM uint8_t SPSC2 : 1;   /*!< [2..2] SRAM Power State Control                                           */
            __IOM uint8_t SPSC3 : 1;   /*!< [3..3] SRAM Power State Control                                           */
            __IOM uint8_t SPSC4 : 1;   /*!< [4..4] SRAM Power State Control                                           */
            __IOM uint8_t SPSC5 : 1;   /*!< [5..5] SRAM Power State Control                                           */
            uint8_t             : 2;
        } SRMPSCR_b;
    };
    __IM uint8_t  RESERVED52;
    __IM uint16_t RESERVED53;
    __IM uint32_t RESERVED54[179];

    union
    {
        __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
                                          *                  Register                                                   */

        struct
        {
            __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
            uint32_t                : 1;
            __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
            __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
            __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
            __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
            __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
            __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
            __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
            uint32_t                : 2;
            __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
            uint32_t                : 4;
            __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
            uint32_t                : 1;
            __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
            uint32_t                : 1;
            __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
            uint32_t                : 5;
            __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non Secure Attribute bit 26                                      */
            __IOM uint32_t NONSEC27 : 1; /*!< [27..27] Non Secure Attribute bit 27                                      */
            uint32_t                : 4;
        } CGFSAR_b;
    };

    union
    {
        __IOM uint32_t RSTSAR;          /*!< (@ 0x000003C4) Reset Security Attribution Register                        */

        struct
        {
            __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
            __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
            __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
            uint32_t               : 29;
        } RSTSAR_b;
    };

    union
    {
        __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */

        struct
        {
            __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
            uint32_t               : 1;
            __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
            uint32_t               : 1;
            __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
            uint32_t               : 27;
        } LPMSAR_b;
    };

    union
    {
        __IOM uint32_t LVDSAR;           /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */

        struct
        {
            __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
            __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
            uint32_t                : 6;
            __IOM uint32_t NONSEC8  : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
            __IOM uint32_t NONSEC9  : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
            __IOM uint32_t NONSEC10 : 1; /*!< [10..10] Non Secure Attribute bit 10                                      */
            uint32_t                : 21;
        } LVDSAR_b;
    };
    __IM uint32_t RESERVED55[11];
    __IM uint16_t RESERVED56;

    union
    {
        __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */

        struct
        {
            __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
                                        *   generation circuit.                                                       */
            __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
                                        *   modes, the low power consumption modes and the battery
                                        *   backup function.                                                          */
            uint16_t            : 1;
            __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
            __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
            uint16_t            : 3;
            __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
        } PRCR_b;
    };
    __IM uint32_t RESERVED57[3];
    __IM uint16_t RESERVED58;

    union
    {
        __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */

        struct
        {
            uint8_t             : 7;
            __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
        } SYOCDCR_b;
    };
    __IM uint8_t RESERVED59;

    union
    {
        __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */

        struct
        {
            __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
                                        *   the flag. Confirm the value is 1 and then write 0.                        */
            __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
                                        *   to clear the flag. Confirm the value is 1 and then write
                                        *   0.                                                                        */
            __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
                                        *   to clear the flag. Confirm the value is 1 and then write
                                        *   0.                                                                        */
            __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
                                        *   to clear the flag. Confirm the value is 1 and then write
                                        *   0.                                                                        */
            uint8_t : 4;
        } RSTSR0_b;
    };

    union
    {
        __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */

        struct
        {
            __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
            uint8_t            : 7;
        } RSTSR2_b;
    };
    __IM uint8_t RESERVED60;

    union
    {
        __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
                                        *                  Register                                                   */

        struct
        {
            uint8_t              : 3;
            __IOM uint8_t MODRV1 : 1;  /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
            uint8_t              : 2;
            __IOM uint8_t MOSEL  : 1;  /*!< [6..6] Main Clock Oscillator Switching                                    */
            uint8_t              : 1;
        } MOMCR_b;
    };
    __IM uint16_t RESERVED61;
    __IM uint8_t  RESERVED62;

    union
    {
        union
        {
            __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */

            struct
            {
                uint8_t             : 5;
                __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
                __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
                uint8_t             : 1;
            } LVCMPCR_b;
        };

        union
        {
            __IOM uint8_t LVD1CMPCR;      /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */

            struct
            {
                __IOM uint8_t LVDLVL : 4; /*!< [3..0] Voltage Detection 1 Level Select (Standard voltage during
                                           *   drop in voltage)                                                          */
                uint8_t            : 3;
                __IOM uint8_t LVDE : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
            } LVD1CMPCR_b;
        };
    };

    union
    {
        __IOM uint8_t LVD2CMPCR;         /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */

        struct
        {
            __IOM uint8_t LVDLVL : 3;    /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
                                          *   drop in voltage)                                                          */
            uint8_t                 : 3;
            __IOM uint8_t EXVCCINP2 : 1; /*!< [6..6] Voltage Detection 2 Comparison (Voltage external input
                                          *   select)                                                                   */
            __IOM uint8_t LVDE : 1;      /*!< [7..7] Voltage Detection 2 Enable                                         */
        } LVD2CMPCR_b;
    };
    __IM uint8_t RESERVED63;

    union
    {
        __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */

        struct
        {
            __IOM uint8_t RIE  : 1;    /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
            uint8_t            : 1;
            __IOM uint8_t CMPE : 1;    /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
            uint8_t            : 3;
            __IOM uint8_t RI   : 1;    /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
            __IOM uint8_t RN   : 1;    /*!< [7..7] Voltage Monitor Reset Negate Select                                */
        } LVD1CR0_b;
    };

    union
    {
        __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */

        struct
        {
            __IOM uint8_t RIE  : 1;    /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
            uint8_t            : 1;
            __IOM uint8_t CMPE : 1;    /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
            uint8_t            : 3;
            __IOM uint8_t RI   : 1;    /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
            __IOM uint8_t RN   : 1;    /*!< [7..7] Voltage Monitor Reset Negate Select                                */
        } LVD2CR0_b;
    };
    __IM uint32_t RESERVED64[25];

    union
    {
        __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */

        struct
        {
            __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
            uint8_t             : 7;
        } SOSCCR_b;
    };

    union
    {
        __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */

        struct
        {
            __IOM uint8_t SODRV  : 2;  /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
            uint8_t              : 2;
            __IOM uint8_t EXCLKS : 1;  /*!< [4..4] Sub Clock Oscillator Mode Function Switching                       */
            uint8_t              : 3;
        } SOMCR_b;
    };

    union
    {
        __IOM uint8_t SOMRG;           /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register                 */

        struct
        {
            __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching                        */
            uint8_t               : 6;
        } SOMRG_b;
    };
    __IM uint8_t  RESERVED65;
    __IM uint32_t RESERVED66[3];

    union
    {
        __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */

        struct
        {
            __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
            uint8_t             : 7;
        } LOCOCR_b;
    };
    __IM uint8_t RESERVED67;

    union
    {
        __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */

        struct
        {
            __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
                                         *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
                                         *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
                                         +126 0111_1111 : +127These bits are added to original LOCO
                                         *   trimming bits                                                             */
        } LOCOUTCR_b;
    };
    __IM uint8_t  RESERVED68;
    __IM uint32_t RESERVED69[11];

    union
    {
        __IOM uint8_t VBTLVDCR;        /*!< (@ 0x000004C0) EXLVDVBAT Circuit Control Register                         */

        struct
        {
            uint8_t            : 4;
            __IOM uint8_t LVDE : 1;    /*!< [4..4] EXLVDVBAT Pin Low Voltage Detect Enable                            */
            __IOM uint8_t LVL  : 3;    /*!< [7..5] EXLVDVBAT Pin Low Voltage Detect Level Select                      */
        } VBTLVDCR_b;
    };

    union
    {
        __IOM uint8_t VBTLVDSR;        /*!< (@ 0x000004C1) EXLVDVBAT Circuit Status Register                          */

        struct
        {
            uint8_t           : 1;
            __IOM uint8_t DET : 1;     /*!< [1..1] EXLVDVBAT Pin Low Voltage Detect Flag                              */
            uint8_t           : 3;
            __IM uint8_t MON  : 1;     /*!< [5..5] EXLVDVBAT Pin Low Voltage Monitor Flag                             */
            uint8_t           : 2;
        } VBTLVDSR_b;
    };

    union
    {
        __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004C2) EXLVDVBAT Comparator Control Register                      */

        struct
        {
            __IOM uint8_t CMPE : 1;    /*!< [0..0] EXLVDVBAT Pin Low Voltage Detect Circuit Output Enable             */
            uint8_t            : 7;
        } VBTCMPCR_b;
    };

    union
    {
        __IOM uint8_t VBTLVDICR;       /*!< (@ 0x000004C3) EXLVDVBAT Pin Low Voltage Detect Interrupt Control
                                        *                  Register                                                   */

        struct
        {
            __IOM uint8_t IE     : 1;  /*!< [0..0] EXLVDVBAT Pin Low Voltage Detect Interrupt Enable                  */
            uint8_t              : 3;
            __IOM uint8_t IDTSEL : 2;  /*!< [5..4] EXLVDVBAT Pin Low Voltage Detect Interrupt Generation
                                        *   Condition Select                                                          */
            uint8_t : 2;
        } VBTLVDICR_b;
    };

    union
    {
        __IOM uint8_t VRTLVDCR;        /*!< (@ 0x000004C4) LVDVRTC Circuit Control Register                           */

        struct
        {
            uint8_t            : 4;
            __IOM uint8_t LVDE : 1;    /*!< [4..4] VRTC Pin Low Voltage Detect Enable                                 */
            __IOM uint8_t LVL  : 3;    /*!< [7..5] VRTC Pin Low Voltage Detect Level Select                           */
        } VRTLVDCR_b;
    };

    union
    {
        __IOM uint8_t VRTSR;           /*!< (@ 0x000004C5) VRTC Status Register                                       */

        struct
        {
            __IOM uint8_t PORDET : 1;  /*!< [0..0] VRTC-domain Power-on Reset Detect Flag                             */
            __IOM uint8_t DET    : 1;  /*!< [1..1] VRTC Voltage Variation Detection Flag                              */
            uint8_t              : 2;
            __IM uint8_t VRTVLD  : 1;  /*!< [4..4] VRTC-domain Valid                                                  */
            __IM uint8_t MON     : 1;  /*!< [5..5] VRTC Signal Monitor Flag                                           */
            uint8_t              : 2;
        } VRTSR_b;
    };

    union
    {
        __IOM uint8_t VRTCMPCR;        /*!< (@ 0x000004C6) VRTC Comparator Control Register                           */

        struct
        {
            __IOM uint8_t CMPE : 1;    /*!< [0..0] VRTC Pin Low Voltage Detect Circuit Output Enable                  */
            uint8_t            : 7;
        } VRTCMPCR_b;
    };

    union
    {
        __IOM uint8_t VRTLVDICR;       /*!< (@ 0x000004C7) VRTC Pin Low Voltage Detect Interrupt Control
                                        *                  Register                                                   */

        struct
        {
            __IOM uint8_t IE     : 1;  /*!< [0..0] VRTC Pin Low Voltage Detect Interrupt Enable                       */
            uint8_t              : 3;
            __IOM uint8_t IDTSEL : 2;  /*!< [5..4] VRTC Pin Low Voltage Detect Interrupt Generation Condition
                                        *   Select                                                                    */
            uint8_t : 2;
        } VRTLVDICR_b;
    };

    union
    {
        __IOM uint8_t EXLVDCR;         /*!< (@ 0x000004C8) EXLVD Circuit Control Register                             */

        struct
        {
            uint8_t            : 4;
            __IOM uint8_t LVDE : 1;    /*!< [4..4] EXLVD Pin Low Voltage Detect Enable                                */
            uint8_t            : 3;
        } EXLVDCR_b;
    };

    union
    {
        __IOM uint8_t EXLVDSR;         /*!< (@ 0x000004C9) EXLVD Circuit Status Register                              */

        struct
        {
            uint8_t           : 1;
            __IOM uint8_t DET : 1;     /*!< [1..1] EXLVD pin Low Voltage Detect Flag                                  */
            uint8_t           : 3;
            __IM uint8_t MON  : 1;     /*!< [5..5] EXLVD pin Low Voltage Monitor Flag                                 */
            uint8_t           : 2;
        } EXLVDSR_b;
    };

    union
    {
        __IOM uint8_t EXLVDCMPCR;      /*!< (@ 0x000004CA) EXLVD Comparator Control Register                          */

        struct
        {
            __IOM uint8_t CMPE : 1;    /*!< [0..0] EXLVD Pin Low Voltage Detect Circuit Output Enable                 */
            uint8_t            : 7;
        } EXLVDCMPCR_b;
    };

    union
    {
        __IOM uint8_t EXLVDICR;        /*!< (@ 0x000004CB) EXLVD Pin Low Voltage Detect Interrupt Control
                                        *                  Register                                                   */

        struct
        {
            __IOM uint8_t IE     : 1;  /*!< [0..0] EXLVD Pin Low Voltage Detect Interrupt Enable                      */
            uint8_t              : 3;
            __IOM uint8_t IDTSEL : 2;  /*!< [5..4] EXLVD Pin Low Voltage Detect Interrupt Generation Condition
                                        *   Select                                                                    */
            uint8_t : 2;
        } EXLVDICR_b;
    };
} R_SYSTEM_Type;                       /*!< Size = 1228 (0x4cc)                                                       */

/* =========================================================================================================================== */
/* ================                                           R_TSN                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Temperature Sensor (R_TSN)
 */

typedef struct                         /*!< (@ 0x407EC000) R_TSN Structure                                            */
{
    __IM uint16_t RESERVED[276];

    union
    {
        __IM uint16_t TSCDR;           /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register               */

        struct
        {
            union
            {
                __IM uint8_t TSCDRL;         /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
                                              *                  L                                                          */

                struct
                {
                    __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
                } TSCDRL_b;
            };

            union
            {
                __IM uint8_t TSCDRH;         /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
                                              *                  H                                                          */

                struct
                {
                    __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the
                                              *   convertedvalue.                                                           */
                } TSCDRH_b;
            };
        };
    };
    __IM uint16_t TSCDRR;              /*!< (@ 0x0000022A) Temperature Sensor Calibration Data Register
                                        *                  (Room Temperature)                                         */
} R_TSN_Type;                          /*!< Size = 556 (0x22c)                                                        */

/* =========================================================================================================================== */
/* ================                                         R_USB_FS0                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief USB 2.0 Module (R_USB_FS0)
 */

typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
{
    union
    {
        __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */

        struct
        {
            __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
            uint16_t             : 2;
            __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
            __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
            __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
            __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
            uint16_t             : 1;
            __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
            uint16_t             : 1;
            __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
            uint16_t             : 5;
        } SYSCFG_b;
    };

    union
    {
        __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */

        struct
        {
            __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
                                        *   access cycles)                                                            */
            uint16_t : 12;
        } BUSWAIT_b;
    };

    union
    {
        __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */

        struct
        {
            __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
            __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
            uint16_t            : 2;
            __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
                                        *   Selected.                                                                 */
            __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
            uint16_t             : 7;
            __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
                                        *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
                                        *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
                                        *   pin.                                                                      */
        } SYSSTS0_b;
    };

    union
    {
        __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */

        struct
        {
            __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
            uint16_t              : 15;
        } PLLSTA_b;
    };

    union
    {
        __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */

        struct
        {
            __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
            uint16_t               : 1;
            __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
            __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
            __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
            __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
            __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
            __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
            __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
            __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
                                         *   used when switching from device B to device A while in
                                         *   OTG mode. If the HNPBTOA bit is 1, the internal function
                                         *   control keeps the suspended state until the HNP processing
                                         *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
                                         *   set.                                                                      */
            uint16_t : 4;
        } DVSTCTR0_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */

        struct
        {
            __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
            uint16_t            : 12;
        } TESTMODE_b;
    };
    __IM uint16_t RESERVED1;
    __IM uint32_t RESERVED2;

    union
    {
        __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */

        struct
        {
            union
            {
                __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
                __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
            };

            union
            {
                __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */

                struct
                {
                    __IM uint8_t  RESERVED3;
                    __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
                };
            };
        };
    };

    union
    {
        __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */

        struct
        {
            union
            {
                __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
                __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
            };

            union
            {
                __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */

                struct
                {
                    __IM uint8_t  RESERVED4;
                    __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
                };
            };
        };
    };

    union
    {
        __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */

        struct
        {
            union
            {
                __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
                __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
            };

            union
            {
                __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */

                struct
                {
                    __IM uint8_t  RESERVED5;
                    __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
                };
            };
        };
    };

    union
    {
        __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */

        struct
        {
            __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
            uint16_t               : 1;
            __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
            uint16_t               : 2;
            __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
            uint16_t               : 1;
            __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
            uint16_t               : 2;
            __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
            __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
        } CFIFOSEL_b;
    };

    union
    {
        __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */

        struct
        {
            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
                                        *   data.                                                                     */
            uint16_t            : 1;
            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
            __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
        } CFIFOCTR_b;
    };
    __IM uint32_t RESERVED6;

    union
    {
        __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */

        struct
        {
            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
            uint16_t               : 4;
            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
            uint16_t               : 1;
            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
                                         *   Pipe Data is Read                                                         */
            __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
        } D0FIFOSEL_b;
    };

    union
    {
        __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */

        struct
        {
            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
                                        *   data.                                                                     */
            uint16_t            : 1;
            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
        } D0FIFOCTR_b;
    };

    union
    {
        __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */

        struct
        {
            __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
            uint16_t               : 4;
            __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
            uint16_t               : 1;
            __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
            __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
            __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
                                         *   Pipe Data is Read                                                         */
            __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
            __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
        } D1FIFOSEL_b;
    };

    union
    {
        __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */

        struct
        {
            __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
                                        *   data.                                                                     */
            uint16_t            : 1;
            __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
            __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
            __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
        } D1FIFOCTR_b;
    };

    union
    {
        __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */

        struct
        {
            uint16_t             : 8;
            __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
            __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
            __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
            __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
            __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
            __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
            __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
            __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
        } INTENB0_b;
    };

    union
    {
        __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */

        struct
        {
            __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
            uint16_t                  : 3;
            __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
            __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
            __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
            uint16_t                  : 4;
            __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
            __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
            uint16_t                  : 1;
            __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
            __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
        } INTENB1_b;
    };
    __IM uint16_t RESERVED7;

    union
    {
        __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */

        struct
        {
            __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
            uint16_t                  : 6;
        } BRDYENB_b;
    };

    union
    {
        __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */

        struct
        {
            __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
            uint16_t                  : 6;
        } NRDYENB_b;
    };

    union
    {
        __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */

        struct
        {
            __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
            __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
            uint16_t                  : 6;
        } BEMPENB_b;
    };

    union
    {
        __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */

        struct
        {
            uint16_t                : 4;
            __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
            __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
            __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
            uint16_t                : 1;
            __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
            uint16_t                : 7;
        } SOFCFG_b;
    };

    union
    {
        __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */

        struct
        {
            __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
            __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
            uint16_t                : 1;
            __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
            __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
            uint16_t                : 2;
            __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
            uint16_t                : 1;
            __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
            uint16_t                : 3;
            __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
        } PHYSET_b;
    };

    union
    {
        __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */

        struct
        {
            __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
            __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
            __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
            __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
            __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
            __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
            __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
            __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
            __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
            __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
            __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
            __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
        } INTSTS0_b;
    };

    union
    {
        __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */

        struct
        {
            __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
            uint16_t                 : 3;
            __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
            __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
            __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
            uint16_t                 : 1;
            __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
            __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
            uint16_t                 : 1;
            __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
            __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
            uint16_t                 : 1;
            __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
            __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
        } INTSTS1_b;
    };
    __IM uint16_t RESERVED8;

    union
    {
        __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */

        struct
        {
            __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
            uint16_t                 : 6;
        } BRDYSTS_b;
    };

    union
    {
        __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */

        struct
        {
            __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
            uint16_t                 : 6;
        } NRDYSTS_b;
    };

    union
    {
        __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */

        struct
        {
            __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
            __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
            uint16_t                 : 6;
        } BEMPSTS_b;
    };

    union
    {
        __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */

        struct
        {
            __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
            uint16_t            : 3;
            __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
            __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
        } FRMNUM_b;
    };

    union
    {
        __IOM uint16_t DVCHGR;         /*!< (@ 0x0000004E) Device State Change Register                               */

        struct
        {
            uint16_t             : 15;
            __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
        } DVCHGR_b;
    };

    union
    {
        __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */

        struct
        {
            __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
                                           *   the USB address assigned by the host when the USBHS processed
                                           *   the SET_ADDRESS request successfully.                                     */
            uint16_t                 : 1;
            __IOM uint16_t STSRECOV0 : 4; /*!< [11..8] Status Recovery                                                   */
            uint16_t                 : 4;
        } USBADDR_b;
    };
    __IM uint16_t RESERVED9;

    union
    {
        __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */

        struct
        {
            __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
                                               *   value.                                                                    */
            __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
        } USBREQ_b;
    };

    union
    {
        __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */

        struct
        {
            __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
        } USBVAL_b;
    };

    union
    {
        __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */

        struct
        {
            __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
        } USBINDX_b;
    };

    union
    {
        __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */

        struct
        {
            __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
        } USBLENG_b;
    };

    union
    {
        __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */

        struct
        {
            uint16_t              : 4;
            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
            uint16_t              : 2;
            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
            __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
            uint16_t              : 7;
        } DCPCFG_b;
    };

    union
    {
        __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */

        struct
        {
            __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
                                        *   of data (maximum packet size) in payloads for the DCP.                    */
            uint16_t              : 5;
            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
        } DCPMAXP_b;
    };

    union
    {
        __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */

        struct
        {
            __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
            __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
            uint16_t                : 2;
            __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
            __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
            __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
            __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
            uint16_t                : 2;
            __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
            uint16_t                : 2;
            __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
            __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
        } DCPCTR_b;
    };
    __IM uint16_t RESERVED10;

    union
    {
        __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */

        struct
        {
            __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
            uint16_t               : 12;
        } PIPESEL_b;
    };
    __IM uint16_t RESERVED11;

    union
    {
        __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */

        struct
        {
            __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
                                        *   for the selected pipe.Setting 0000b means unused pipe.                    */
            __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
            uint16_t              : 2;
            __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
            uint16_t              : 1;
            __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
            __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
            uint16_t              : 3;
            __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
        } PIPECFG_b;
    };
    __IM uint16_t RESERVED12;

    union
    {
        __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */

        struct
        {
            __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
                                        *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
                                        *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
                                        *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
                                        *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
            uint16_t              : 3;
            __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
        } PIPEMAXP_b;
    };

    union
    {
        __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */

        struct
        {
            __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
                                        *   error detection timing for the selected pipe in terms of
                                        *   frames, which is expressed as nth power of 2.                             */
            uint16_t            : 9;
            __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
            uint16_t            : 3;
        } PIPEPERI_b;
    };

    union
    {
        __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */

        struct
        {
            __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
            uint16_t              : 3;
            __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
            __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
            __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
            __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
            __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
            __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
            uint16_t              : 1;
            __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
                                        *   Split Transaction of the relevant pipe                                    */
            __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
                                        *   the CSSTS bit of the relevant pipe                                        */
            __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
            __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
        } PIPE_CTR_b[9];
    };
    __IM uint16_t                RESERVED13;
    __IM uint32_t                RESERVED14[3];
    __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
    __IM uint32_t                RESERVED15[3];

    union
    {
        __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */

        struct
        {
            __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
            __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
            __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
            __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
            __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
            __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
            uint16_t                  : 1;
            __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
            __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
            __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
            uint16_t                  : 6;
        } USBBCCTRL0_b;
    };
    __IM uint16_t RESERVED16;
    __IM uint32_t RESERVED17[4];

    union
    {
        __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */

        struct
        {
            __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
            uint16_t               : 15;
        } UCKSEL_b;
    };
    __IM uint16_t RESERVED18;
    __IM uint32_t RESERVED19;

    union
    {
        __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */

        struct
        {
            __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
            uint16_t               : 6;
            __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
            uint16_t               : 8;
        } USBMC_b;
    };
    __IM uint16_t RESERVED20;

    union
    {
        __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */

        struct
        {
            uint16_t               : 6;
            __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
            __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
            __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
            uint16_t               : 1;
        } DEVADD_b[10];
    };
    __IM uint32_t RESERVED21[3];

    union
    {
        __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */

        struct
        {
            __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
            __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
            __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
            __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
            uint32_t               : 28;
        } PHYSLEW_b;
    };
    __IM uint32_t RESERVED22[3];

    union
    {
        __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */

        struct
        {
            uint16_t             : 7;
            __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
            uint16_t             : 8;
        } LPCTRL_b;
    };

    union
    {
        __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */

        struct
        {
            uint16_t                : 14;
            __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
            uint16_t                : 1;
        } LPSTS_b;
    };
    __IM uint32_t RESERVED23[15];

    union
    {
        __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */

        struct
        {
            __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
            __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
            __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
            __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
            __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
            __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
            uint16_t                : 2;
            __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
            __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
            uint16_t                : 6;
        } BCCTRL_b;
    };
    __IM uint16_t RESERVED24;

    union
    {
        __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */

        struct
        {
            __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
            __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
            __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
                                          *   only when the L1RESPMD[1:0] value is 2'b11.                               */
            __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
                                          *   the L1 state together with the device state bits DVSQ[2:0].               */
            __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
                                          *   value used for L1NEGOMD.The format is the same as the HIRD
                                          *   field in HL1CTRL.                                                         */
            uint16_t               : 2;
            __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
            uint16_t               : 1;
        } PL1CTRL1_b;
    };

    union
    {
        __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */

        struct
        {
            uint16_t               : 8;
            __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
            __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
            uint16_t               : 3;
        } PL1CTRL2_b;
    };

    union
    {
        __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */

        struct
        {
            __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
            __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
            uint16_t                : 13;
        } HL1CTRL1_b;
    };

    union
    {
        __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */

        struct
        {
            __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
                                        *   be set in the ADDR field of LPM token.                                    */
            uint16_t             : 4;
            __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
            __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
                                        *   value to be set in the RWE field of LPM token.                            */
            uint16_t            : 2;
            __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
                                        *   period at the time of L1 Resume.                                          */
        } HL1CTRL2_b;
    };
    __IM uint32_t RESERVED25[5];

    union
    {
        __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
                                        *                  Register                                                   */

        struct
        {
            uint32_t              : 20;
            __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
                                         *   HS side of USB port.                                                      */
            __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
                                         *   HS side of USB port.                                                      */
            uint32_t               : 1;
            __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
                                         *   of USB port.                                                              */
            uint32_t : 8;
        } DPUSR0R_b;
    };

    union
    {
        __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */

        struct
        {
            uint32_t                : 4;
            __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
            __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
            uint32_t                : 1;
            __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
            uint32_t                : 12;
            __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
            __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
            uint32_t                : 1;
            __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
            uint32_t                : 8;
        } DPUSR1R_b;
    };

    union
    {
        __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */

        struct
        {
            __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
            __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
            uint16_t            : 2;
            __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
                                        *   port.                                                                     */
            __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
                                        *   port.                                                                     */
            uint16_t              : 2;
            __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
            __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
            uint16_t              : 6;
        } DPUSR2R_b;
    };

    union
    {
        __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */

        struct
        {
            __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
            __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
            uint16_t                : 14;
        } DPUSRCR_b;
    };
    __IM uint32_t RESERVED26[165];

    union
    {
        __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
                                         *                  Monitor Register                                           */

        struct
        {
            __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
            __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
            uint32_t               : 1;
            __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
            __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
            uint32_t               : 11;
            __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
            __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
            uint32_t               : 2;
            __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
                                         *   of the USB.                                                               */
            __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
                                         *   of the USB.                                                               */
            uint32_t              : 1;
            __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
                                         *   USB.                                                                      */
            uint32_t : 8;
        } DPUSR0R_FS_b;
    };

    union
    {
        __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
                                           *                  Register                                                   */

        struct
        {
            __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
            __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
            uint32_t                 : 2;
            __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
            __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
            uint32_t                 : 1;
            __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
            uint32_t                 : 8;
            __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
            __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
            uint32_t                 : 2;
            __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
            __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
            uint32_t                 : 1;
            __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
            uint32_t                 : 8;
        } DPUSR1R_FS_b;
    };
} R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */

/* =========================================================================================================================== */
/* ================                                         R_UARTA0                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Serial Interface UARTA (R_UARTA0)
 */

typedef struct                         /*!< (@ 0x40097000) R_UARTA0 Structure                                         */
{
    __IOM uint8_t TXBAn;               /*!< (@ 0x00000000) Transmit Buffer Register 0                                 */
    __IM uint8_t  RXBAn;               /*!< (@ 0x00000001) Receive Buffer Register 0                                  */

    union
    {
        __IOM uint8_t ASIMAn0;         /*!< (@ 0x00000002) Operation Mode Setting Register 00                         */

        struct
        {
            __IOM uint8_t ISRMA : 1;   /*!< [0..0] Receive Interrupt Mode Select                                      */
            __IOM uint8_t ISSMA : 1;   /*!< [1..1] Transmit Interrupt Mode Select                                     */
            uint8_t             : 3;
            __IOM uint8_t RXEA  : 1;   /*!< [5..5] Reception Enable                                                   */
            __IOM uint8_t TXEA  : 1;   /*!< [6..6] Transmission Enable                                                */
            __IOM uint8_t EN    : 1;   /*!< [7..7] UART Operation Enable                                              */
        } ASIMAn0_b;
    };

    union
    {
        __IOM uint8_t ASIMAn1;         /*!< (@ 0x00000003) Operation Mode Setting Register 01                         */

        struct
        {
            __IOM uint8_t ALV : 1;     /*!< [0..0] Transmission and Reception Level Setting                           */
            __IOM uint8_t DIR : 1;     /*!< [1..1] Transmission and Reception Order Setting                           */
            __IOM uint8_t SL  : 1;     /*!< [2..2] Transmission Stop Bit Length Setting                               */
            __IOM uint8_t CL  : 2;     /*!< [4..3] Transmission and Reception Character Length Setting                */
            __IOM uint8_t PS  : 2;     /*!< [6..5] Transmission and Reception Parity Bit Setting                      */
            uint8_t           : 1;
        } ASIMAn1_b;
    };
    __IOM uint8_t BRGCAn;              /*!< (@ 0x00000004) Baud Rate Generator Control Register 0                     */

    union
    {
        __IM uint8_t ASISAn;           /*!< (@ 0x00000005) Status Register 0                                          */

        struct
        {
            __IM uint8_t OVEA  : 1;    /*!< [0..0] Overrun Error Flag                                                 */
            __IM uint8_t FEA   : 1;    /*!< [1..1] Framing Error Flag                                                 */
            __IM uint8_t PEA   : 1;    /*!< [2..2] Parity Error Flag                                                  */
            uint8_t            : 1;
            __IM uint8_t TXSFA : 1;    /*!< [4..4] Transmit Shift Register Data Flag                                  */
            __IM uint8_t TXBFA : 1;    /*!< [5..5] Transmit Buffer Data Flag                                          */
            uint8_t            : 2;
        } ASISAn_b;
    };

    union
    {
        __IOM uint8_t ASCTAn;          /*!< (@ 0x00000006) Status Clear Trigger Register 0                            */

        struct
        {
            __IOM uint8_t OVECTA : 1;  /*!< [0..0] Overrun Error Flag Clear Trigger                                   */
            __IOM uint8_t FECTA  : 1;  /*!< [1..1] Framing Error Flag Clear Trigger                                   */
            __IOM uint8_t PECTA  : 1;  /*!< [2..2] Parity Error Flag Clear Trigger                                    */
            uint8_t              : 5;
        } ASCTAn_b;
    };
} R_UARTA0_Type;                       /*!< Size = 7 (0x7)                                                            */

/* =========================================================================================================================== */
/* ================                                        R_UARTA_CK                                         ================ */
/* =========================================================================================================================== */

/**
 * @brief Serial Interface UARTA Clock (R_UARTA_CK)
 */

typedef struct                         /*!< (@ 0x40097010) R_UARTA_CK Structure                                       */
{
    union
    {
        __IOM uint8_t UTAnCK[2];       /*!< (@ 0x00000000) UARTA Clock Select Register                                */

        struct
        {
            __IOM uint8_t CK  : 4;     /*!< [3..0] UARTAn Operation Clock Select (fUTAn)                              */
            __IOM uint8_t SEL : 2;     /*!< [5..4] fSEL Clock Select                                                  */
            uint8_t           : 1;
            __IOM uint8_t EN  : 1;     /*!< [7..7] UARTAn clock output function enable                                */
        } UTAnCK_b[2];
    };
} R_UARTA_CK_Type;                     /*!< Size = 2 (0x2)                                                            */

/* =========================================================================================================================== */
/* ================                                           R_WDT                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief Watchdog Timer (R_WDT)
 */

typedef struct                         /*!< (@ 0x40083400) R_WDT Structure                                            */
{
    union
    {
        __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */

        struct
        {
            __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
                                        *   of the WDT.                                                               */
        } WDTRR_b;
    };
    __IM uint8_t RESERVED;

    union
    {
        __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */

        struct
        {
            __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
            uint16_t            : 2;
            __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
            __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
            uint16_t            : 2;
            __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
            uint16_t            : 2;
        } WDTCR_b;
    };

    union
    {
        __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */

        struct
        {
            __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
            __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
            __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
        } WDTSR_b;
    };

    union
    {
        __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */

        struct
        {
            uint8_t               : 7;
            __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
        } WDTRCR_b;
    };
    __IM uint8_t RESERVED1;

    union
    {
        __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */

        struct
        {
            uint8_t              : 7;
            __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
        } WDTCSTPR_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;
} R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */

/* =========================================================================================================================== */
/* ================                                           R_TZF                                           ================ */
/* =========================================================================================================================== */

/**
 * @brief TrustZone Filter (R_TZF)
 */

typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
{
    union
    {
        __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */

        struct
        {
            __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
            uint16_t           : 7;
            __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
        } TZFOAD_b;
    };
    __IM uint16_t RESERVED;

    union
    {
        __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */

        struct
        {
            __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
            uint16_t               : 7;
            __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
        } TZFPT_b;
    };
} R_TZF_Type;                           /*!< Size = 6 (0x6)                                                            */

/* =========================================================================================================================== */
/* ================                                          R_CACHE                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief R_CACHE (R_CACHE)
 */

typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
{
    union
    {
        __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */

        struct
        {
            __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
            uint32_t           : 31;
        } CCACTL_b;
    };

    union
    {
        __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */

        struct
        {
            __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
            uint32_t          : 31;
        } CCAFCT_b;
    };

    union
    {
        __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */

        struct
        {
            __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
            uint32_t          : 30;
        } CCALCF_b;
    };
    __IM uint32_t RESERVED[13];

    union
    {
        __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */

        struct
        {
            __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
            uint32_t           : 31;
        } SCACTL_b;
    };

    union
    {
        __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */

        struct
        {
            __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
            uint32_t          : 31;
        } SCAFCT_b;
    };

    union
    {
        __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */

        struct
        {
            __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
            uint32_t          : 30;
        } SCALCF_b;
    };
    __IM uint32_t RESERVED1[109];

    union
    {
        __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
                                        *                  Register                                                   */

        struct
        {
            __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
            uint32_t           : 31;
        } CAPOAD_b;
    };

    union
    {
        __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */

        struct
        {
            __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
            __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
            uint32_t            : 24;
        } CAPRCR_b;
    };
} R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */

/* =========================================================================================================================== */
/* ================                                          R_CPSCU                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief CPU System Security Control Unit (R_CPSCU)
 */

typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
{
    union
    {
        __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */

        struct
        {
            __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
            __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
            __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
            uint32_t                : 29;
        } CSAR_b;
    };
    __IM uint32_t RESERVED[3];

    union
    {
        __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */

        struct
        {
            __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
            __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
                                         *   2                                                                         */
            __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
            uint32_t               : 29;
        } SRAMSAR_b;
    };

    union
    {
        __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */

        struct
        {
            __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
            uint32_t               : 28;
        } STBRAMSAR_b;
    };
    __IM uint32_t RESERVED1[6];

    union
    {
        __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */

        struct
        {
            __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
            uint32_t               : 31;
        } DTCSAR_b;
    };

    union
    {
        __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */

        struct
        {
            __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
            uint32_t               : 31;
        } DMACSAR_b;
    };
    __IM uint32_t RESERVED2[2];

    union
    {
        __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */

        struct
        {
            __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
            uint32_t                : 16;
        } ICUSARA_b;
    };

    union
    {
        __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */

        struct
        {
            __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
            uint32_t             : 31;
        } ICUSARB_b;
    };

    union
    {
        __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */

        struct
        {
            __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
            uint32_t               : 24;
        } ICUSARC_b;
    };

    union
    {
        __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */

        struct
        {
            __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
            uint32_t                : 31;
        } ICUSARD_b;
    };

    union
    {
        __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */

        struct
        {
            uint32_t                    : 16;
            __IOM uint32_t SAIWDTWUP    : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
            uint32_t                    : 1;
            __IOM uint32_t SALVD1WUP    : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
            __IOM uint32_t SALVD2WUP    : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
            __IOM uint32_t SAVBATTWUP   : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
            uint32_t                    : 2;
            __IOM uint32_t SAACMPLP0WUP : 1; /*!< [23..23] Security attributes of registers for WUPEN0.b 23                 */
            __IOM uint32_t SARTCALMWUP  : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
            __IOM uint32_t SARTCPRDWUP  : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
            uint32_t                    : 1;
            __IOM uint32_t SAUSBFS0WUP  : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
            __IOM uint32_t SAAGT1UDWUP  : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
            __IOM uint32_t SAAGT1CAWUP  : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
            __IOM uint32_t SAAGT1CBWUP  : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
            __IOM uint32_t SAIIC0WUP    : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
        } ICUSARE_b;
    };

    union
    {
        __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */

        struct
        {
            __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
            __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
            __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
            __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
            uint32_t                    : 3;
            __IOM uint32_t SASOSCWUP    : 1; /*!< [7..7] Security attributes of registers for WUPEN1.b 7                    */
            __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
            __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
            __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
            __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
            __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
            __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
            __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
            uint32_t                    : 17;
        } ICUSARF_b;
    };

    union
    {
        __IOM uint32_t ICUSARM;                /*!< (@ 0x00000058) ICU Security Attribution Register M                        */

        struct
        {
            __IOM uint32_t SAINTUR0WUP    : 1; /*!< [0..0] Security attributes of registers for WUPEN2.b 0                    */
            __IOM uint32_t SAINTURE0WUP   : 1; /*!< [1..1] Security attributes of registers for WUPEN2.b 1                    */
            __IOM uint32_t SAINTUR1WUP    : 1; /*!< [2..2] Security attributes of registers for WUPEN2.b 2                    */
            __IOM uint32_t SAINTURE1WUP   : 1; /*!< [3..3] Security attributes of registers for WUPEN2.b 3                    */
            __IOM uint32_t SAEXLVDVBATWUP : 1; /*!< [4..4] Security attributes of registers for WUPEN2.b 4                    */
            __IOM uint32_t SALVDVRTCWUP   : 1; /*!< [5..5] Security attributes of registers for WUPEN2.b 5                    */
            __IOM uint32_t SAEXLVDWUP     : 1; /*!< [6..6] Security attributes of registers for WUPEN2.b 6                    */
            uint32_t                      : 25;
        } ICUSARM_b;
    };
    __IM uint32_t RESERVED3[5];

    union
    {
        __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */

        struct
        {
            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
        } ICUSARG_b;
    };

    union
    {
        __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */

        struct
        {
            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
        } ICUSARH_b;
    };

    union
    {
        __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */

        struct
        {
            __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
        } ICUSARI_b;
    };
    __IM uint32_t RESERVED4[33];

    union
    {
        __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */

        struct
        {
            __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
            uint32_t              : 31;
        } BUSSARA_b;
    };

    union
    {
        __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */

        struct
        {
            __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
            uint32_t              : 31;
        } BUSSARB_b;
    };
    __IM uint32_t RESERVED5[2];

    union
    {
        __IOM uint32_t BUSSARC;        /*!< (@ 0x00000110) Bus Security Attribution Register C                        */

        struct
        {
            __IOM uint32_t BUSSC0 : 1; /*!< [0..0] Bus Security Attribution C0                                        */
            uint32_t              : 31;
        } BUSSARC_b;
    };

    union
    {
        __IOM uint32_t BUSPARC;        /*!< (@ 0x00000114) Bus Privileged Attribution Register C                      */

        struct
        {
            __IOM uint32_t BUSPA0 : 1; /*!< [0..0] External bus controller privilege attribution                      */
            uint32_t              : 31;
        } BUSPARC_b;
    };
    __IM uint32_t RESERVED6[6];

    union
    {
        __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
                                          *                  Register A                                                 */

        struct
        {
            __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
            uint32_t                : 24;
        } MMPUSARA_b;
    };

    union
    {
        __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
                                          *                  Register B                                                 */

        struct
        {
            __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
            uint32_t                : 31;
        } MMPUSARB_b;
    };
    __IM uint32_t RESERVED7[18];

    union
    {
        union
        {
            __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */

            struct
            {
                __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
                uint32_t              : 31;
            } TZFSAR_b;
        };

        union
        {
            __IOM uint32_t DEBUGSAR;       /*!< (@ 0x00000180) Debug Security Attribution Register                        */

            struct
            {
                __IOM uint32_t DBGSA0 : 1; /*!< [0..0] Debug Resources Security Attribution 0                             */
                uint32_t              : 31;
            } DEBUGSAR_b;
        };
    };
    __IM uint32_t RESERVED8[7];

    union
    {
        __IOM uint32_t DMACCHSAR;          /*!< (@ 0x000001A0) DMA channel Security Attribution Register                  */

        struct
        {
            __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
                                            *   channel                                                                   */
            uint32_t : 24;
        } DMACCHSAR_b;
    };
    __IM uint32_t RESERVED9[3];

    union
    {
        __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */

        struct
        {
            __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
            uint32_t               : 31;
        } CPUDSAR_b;
    };
    __IM uint32_t RESERVED10[147];

    union
    {
        __IOM uint32_t SRAMSABAR0;     /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
                                        *                  0                                                          */

        struct
        {
            uint32_t                 : 13;
            __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
                                           *   address of non-secure region).                                            */
            uint32_t : 11;
        } SRAMSABAR0_b;
    };

    union
    {
        __IOM uint32_t SRAMSABAR1;     /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
                                        *                  1                                                          */

        struct
        {
            uint32_t                 : 13;
            __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
                                           *   address of non-secure region).                                            */
            uint32_t : 11;
        } SRAMSABAR1_b;
    };
    __IM uint32_t RESERVED11[126];

    union
    {
        __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */

        struct
        {
            __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
                                        *   and ELCSRn                                                                */
            uint32_t : 31;
        } TEVTRCR_b;
    };
} R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */

/* =========================================================================================================================== */
/* ================                                          R_DOC_B                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Data Operation Circuit (R_DOC_B)
 */

typedef struct                         /*!< (@ 0x40109000) R_DOC_B Structure                                          */
{
    union
    {
        __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */

        struct
        {
            __IOM uint8_t OMS   : 2;   /*!< [1..0] Operating Mode Select                                              */
            uint8_t             : 1;
            __IOM uint8_t DOBW  : 1;   /*!< [3..3] Data Operation Bit Width Select                                    */
            __IOM uint8_t DCSEL : 3;   /*!< [6..4] Detection Condition Select                                         */
            uint8_t             : 1;
        } DOCR_b;
    };
    __IM uint8_t  RESERVED;
    __IM uint16_t RESERVED1;

    union
    {
        __IOM uint8_t DOSR;            /*!< (@ 0x00000004) DOC Flag Status Register                                   */

        struct
        {
            __IM uint8_t DOPCF : 1;    /*!< [0..0] Data Operation Circuit Flag                                        */
            uint8_t            : 7;
        } DOSR_b;
    };
    __IM uint8_t  RESERVED2;
    __IM uint16_t RESERVED3;

    union
    {
        __IOM uint8_t DOSCR;           /*!< (@ 0x00000008) DOC Flag Status Clear Register                             */

        struct
        {
            __OM uint8_t DOPCFCL : 1;  /*!< [0..0] DOPCF Clear                                                        */
            uint8_t              : 7;
        } DOSCR_b;
    };
    __IM uint8_t   RESERVED4;
    __IM uint16_t  RESERVED5;
    __IOM uint32_t DODIR;              /*!< (@ 0x0000000C) DOC Data Input Register                                    */
    __IOM uint32_t DODSR0;             /*!< (@ 0x00000010) DOC Data Setting Register 0                                */
    __IOM uint32_t DODSR1;             /*!< (@ 0x00000014) DOC Data Setting Register 1                                */
} R_DOC_B_Type;                        /*!< Size = 24 (0x18)                                                          */

/* =========================================================================================================================== */
/* ================                                          R_AGTX0                                          ================ */
/* =========================================================================================================================== */

/**
 * @brief Asynchronous General Purpose Timer (R_AGTX0)
 */

typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
{
    union
    {
        __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
        __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
    };
} R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */

/** @} */ /* End of group Device_Peripheral_peripherals */

/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */

/** @addtogroup Device_Peripheral_peripheralAddr
 * @{
 */

 #define R_ACMPLP_BASE         0x400F4000UL
 #define R_ADC0_BASE           0x40170000UL
 #define R_ADC1_BASE           0x40170200UL
 #define R_PSCU_BASE           0x400E0000UL
 #define R_BUS_BASE            0x40003000UL
 #define R_CAC_BASE            0x40083600UL
 #define R_CANFD_BASE          0x400B0000UL
 #define R_CANFD1_BASE         0x400B2000UL
 #define R_CRC_BASE            0x40108000UL
 #define R_CTSU2_BASE          0x400D0000UL
 #define R_DAC_BASE            0x40171000UL
 #define R_DEBUG_BASE          0x4001B000UL
 #define R_DMA_BASE            0x40005200UL
 #define R_DMAC0_BASE          0x40005000UL
 #define R_DMAC1_BASE          0x40005040UL
 #define R_DMAC2_BASE          0x40005080UL
 #define R_DMAC3_BASE          0x400050C0UL
 #define R_DMAC4_BASE          0x40005100UL
 #define R_DMAC5_BASE          0x40005140UL
 #define R_DMAC6_BASE          0x40005180UL
 #define R_DMAC7_BASE          0x400051C0UL
 #define R_DTC_BASE            0x40005400UL
 #define R_ELC_BASE            0x40082000UL
 #define R_FACI_HP_CMD_BASE    0x407E0000UL
 #define R_FACI_HP_BASE        0x407FE000UL
 #define R_FACI_LP_BASE        0x407EC000UL
 #define R_CTSUTRIM_BASE       0x407EC000UL
 #define R_FCACHE_BASE         0x4001C000UL
 #define R_GPT0_BASE           0x40169000UL
 #define R_GPT1_BASE           0x40169100UL
 #define R_GPT2_BASE           0x40169200UL
 #define R_GPT3_BASE           0x40169300UL
 #define R_GPT4_BASE           0x40169400UL
 #define R_GPT5_BASE           0x40169500UL
 #define R_GPT6_BASE           0x40169600UL
 #define R_GPT7_BASE           0x40169700UL
 #define R_GPT8_BASE           0x40169800UL
 #define R_GPT9_BASE           0x40169900UL
 #define R_GPT10_BASE          0x40169A00UL
 #define R_GPT11_BASE          0x40169B00UL
 #define R_GPT12_BASE          0x40169C00UL
 #define R_GPT13_BASE          0x40169D00UL
 #define R_GPT_OPS_BASE        0x40169A00UL
 #define R_GPT_POEG0_BASE      0x4008A000UL
 #define R_GPT_POEG1_BASE      0x4008A100UL
 #define R_GPT_POEG2_BASE      0x4008A200UL
 #define R_GPT_POEG3_BASE      0x4008A300UL
 #define R_ICU_BASE            0x40006000UL
 #define R_IIC0_BASE           0x4009F000UL
 #define R_IIC1_BASE           0x4009F100UL
 #define R_IIC2_BASE           0x4009F200UL
 #define R_IRDA_BASE           0x40118F00UL
 #define R_IWDT_BASE           0x40083200UL
 #define R_I3C0_BASE           0x4011F000UL
 #define R_I3C1_BASE           0x4011F400UL
 #define R_MPU_MMPU_BASE       0x40000000UL
 #define R_MPU_SPMON_BASE      0x40000D00UL
 #define R_MSTP_BASE           0x40084000UL
 #define R_PORT0_BASE          0x4001F000UL
 #define R_PORT1_BASE          0x4001F020UL
 #define R_PORT2_BASE          0x4001F040UL
 #define R_PORT3_BASE          0x4001F060UL
 #define R_PORT4_BASE          0x4001F080UL
 #define R_PORT5_BASE          0x4001F0A0UL
 #define R_PORT6_BASE          0x4001F0C0UL
 #define R_PORT7_BASE          0x4001F0E0UL
 #define R_PORT8_BASE          0x4001F100UL
 #define R_PORT9_BASE          0x40080120UL
 #define R_PORT10_BASE         0x40080140UL
 #define R_PORT11_BASE         0x40080160UL
 #define R_PORT12_BASE         0x40080180UL
 #define R_PORT13_BASE         0x400801A0UL
 #define R_PORT14_BASE         0x400801C0UL
 #define R_PFS_BASE            0x4001F800UL
 #define R_PMISC_BASE          0x4001FD00UL
 #define R_QSPI_BASE           0x64000000UL
 #define R_RTC_BASE            0x40083000UL
 #define R_SCI0_BASE           0x40118000UL
 #define R_SCI1_BASE           0x40118100UL
 #define R_SCI2_BASE           0x40118200UL
 #define R_SCI3_BASE           0x40118300UL
 #define R_SCI4_BASE           0x40118400UL
 #define R_SCI5_BASE           0x40118500UL
 #define R_SCI6_BASE           0x40118600UL
 #define R_SCI7_BASE           0x40118700UL
 #define R_SCI8_BASE           0x40118800UL
 #define R_SCI9_BASE           0x40118900UL
 #define R_SLCDC_BASE          0x400D4000UL
 #define R_SPI0_BASE           0x4011A000UL
 #define R_SPI1_BASE           0x4011A100UL
 #define R_SPI2_BASE           0x40072200UL
 #define R_SRAM_BASE           0x40002000UL
 #define R_SSI0_BASE           0x4009D000UL
 #define R_SSI1_BASE           0x4009D100UL
 #define R_SYSTEM_BASE         0x4001E000UL
 #define R_TSN_BASE            0x407EC000UL
 #define R_USB_FS0_BASE        0x40090000UL
 #define R_UARTA0_BASE         0x40097000UL
 #define R_UARTA1_BASE         0x40097008UL
 #define R_UARTA_CK_BASE       0x40097010UL
 #define R_WDT_BASE            0x40083400UL
 #define R_TZF_BASE            0x40000E00UL
 #define R_CACHE_BASE          0x40007000UL
 #define R_CPSCU_BASE          0x40008000UL
 #define R_DOC_B_BASE          0x40109000UL
 #define R_AGTX0_BASE          0x400E8000UL
 #define R_AGTX1_BASE          0x400E8100UL
 #define R_AGTX2_BASE          0x400E8200UL
 #define R_AGTX3_BASE          0x400E8300UL
 #define R_AGTX4_BASE          0x400E8400UL
 #define R_AGTX5_BASE          0x400E8500UL
 #define R_AGTX6_BASE          0x400E8600UL
 #define R_AGTX7_BASE          0x400E8700UL
 #define R_AGTX8_BASE          0x400E8800UL
 #define R_AGTX9_BASE          0x400E8900UL
 #define R_WDT1_BASE           0x40044300UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */

/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */

/** @addtogroup Device_Peripheral_declaration
 * @{
 */

 #define R_ACMPLP         ((R_ACMPLP_Type *) R_ACMPLP_BASE)
 #define R_ADC0           ((R_ADC0_Type *) R_ADC0_BASE)
 #define R_ADC1           ((R_ADC0_Type *) R_ADC1_BASE)
 #define R_PSCU           ((R_PSCU_Type *) R_PSCU_BASE)

/* #define R_BUS                       ((R_BUS_Type*)             R_BUS_BASE) */
 #define R_CAC            ((R_CAC_Type *) R_CAC_BASE)
 #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
 #define R_CANFD0         ((R_CANFD_Type *) R_CANFD_BASE)
 #define R_CANFD1         ((R_CANFD_Type *) R_CANFD1_BASE)
 #define R_CRC            ((R_CRC_Type *) R_CRC_BASE)
 #define R_CTSU           ((R_CTSU2_Type *) R_CTSU2_BASE)
 #define R_DAC            ((R_DAC_Type *) R_DAC_BASE)
 #define R_DEBUG          ((R_DEBUG_Type *) R_DEBUG_BASE)
 #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
 #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
 #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
 #define R_DMAC2          ((R_DMAC0_Type *) R_DMAC2_BASE)
 #define R_DMAC3          ((R_DMAC0_Type *) R_DMAC3_BASE)
 #define R_DMAC4          ((R_DMAC0_Type *) R_DMAC4_BASE)
 #define R_DMAC5          ((R_DMAC0_Type *) R_DMAC5_BASE)
 #define R_DMAC6          ((R_DMAC0_Type *) R_DMAC6_BASE)
 #define R_DMAC7          ((R_DMAC0_Type *) R_DMAC7_BASE)
 #define R_DTC            ((R_DTC_Type *) R_DTC_BASE)
 #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
 #define R_FACI_HP_CMD    ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
 #define R_FACI_HP        ((R_FACI_HP_Type *) R_FACI_HP_BASE)
 #define R_FACI_LP        ((R_FACI_LP_Type *) R_FACI_LP_BASE)
 #define R_CTSUTRIM       ((R_CTSUTRIM_Type *) R_CTSUTRIM_BASE)
 #define R_FCACHE         ((R_FCACHE_Type *) R_FCACHE_BASE)
 #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
 #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
 #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
 #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
 #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
 #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
 #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
 #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
 #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
 #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
 #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
 #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
 #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
 #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
 #define R_GPT_OPS        ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
 #define R_GPT_POEG0      ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
 #define R_GPT_POEG1      ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
 #define R_GPT_POEG2      ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
 #define R_GPT_POEG3      ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
 #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
 #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
 #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
 #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
 #define R_IRDA           ((R_IRDA_Type *) R_IRDA_BASE)
 #define R_IWDT           ((R_IWDT_Type *) R_IWDT_BASE)
 #define R_I3C0           ((R_I3C0_Type *) R_I3C0_BASE)
 #define R_I3C1           ((R_I3C0_Type *) R_I3C1_BASE)
 #define R_MPU_MMPU       ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
 #define R_MPU_SPMON      ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
 #define R_MSTP           ((R_MSTP_Type *) R_MSTP_BASE)
 #define R_PORT0          ((R_PORT0_Type *) R_PORT0_BASE)
 #define R_PORT1          ((R_PORT0_Type *) R_PORT1_BASE)
 #define R_PORT2          ((R_PORT0_Type *) R_PORT2_BASE)
 #define R_PORT3          ((R_PORT0_Type *) R_PORT3_BASE)
 #define R_PORT4          ((R_PORT0_Type *) R_PORT4_BASE)
 #define R_PORT5          ((R_PORT0_Type *) R_PORT5_BASE)
 #define R_PORT6          ((R_PORT0_Type *) R_PORT6_BASE)
 #define R_PORT7          ((R_PORT0_Type *) R_PORT7_BASE)
 #define R_PORT8          ((R_PORT0_Type *) R_PORT8_BASE)
 #define R_PORT9          ((R_PORT0_Type *) R_PORT9_BASE)
 #define R_PORT10         ((R_PORT0_Type *) R_PORT10_BASE)
 #define R_PORT11         ((R_PORT0_Type *) R_PORT11_BASE)
 #define R_PORT12         ((R_PORT0_Type *) R_PORT12_BASE)
 #define R_PORT13         ((R_PORT0_Type *) R_PORT13_BASE)
 #define R_PORT14         ((R_PORT0_Type *) R_PORT14_BASE)
 #define R_PFS            ((R_PFS_Type *) R_PFS_BASE)
 #define R_PMISC          ((R_PMISC_Type *) R_PMISC_BASE)
 #define R_QSPI           ((R_QSPI_Type *) R_QSPI_BASE)
 #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
 #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
 #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
 #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
 #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
 #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
 #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
 #define R_SCI6           ((R_SCI0_Type *) R_SCI6_BASE)
 #define R_SCI7           ((R_SCI0_Type *) R_SCI7_BASE)
 #define R_SCI8           ((R_SCI0_Type *) R_SCI8_BASE)
 #define R_SCI9           ((R_SCI0_Type *) R_SCI9_BASE)
 #define R_SLCDC          ((R_SLCDC_Type *) R_SLCDC_BASE)
 #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
 #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
 #define R_SPI2           ((R_SPI0_Type *) R_SPI2_BASE)
 #define R_SRAM           ((R_SRAM_Type *) R_SRAM_BASE)
 #define R_SSI0           ((R_SSI0_Type *) R_SSI0_BASE)
 #define R_SSI1           ((R_SSI0_Type *) R_SSI1_BASE)
 #define R_SYSTEM         ((R_SYSTEM_Type *) R_SYSTEM_BASE)
 #define R_TSN            ((R_TSN_Type *) R_TSN_BASE)
 #define R_USB_FS0        ((R_USB_FS0_Type *) R_USB_FS0_BASE)
 #define R_UARTA0         ((R_UARTA0_Type *) R_UARTA0_BASE)
 #define R_UARTA1         ((R_UARTA0_Type *) R_UARTA1_BASE)
 #define R_UARTA_CK       ((R_UARTA_CK_Type *) R_UARTA_CK_BASE)
 #define R_WDT            ((R_WDT_Type *) R_WDT_BASE)
 #define R_TZF            ((R_TZF_Type *) R_TZF_BASE)
 #define R_CACHE          ((R_CACHE_Type *) R_CACHE_BASE)
 #define R_CPSCU          ((R_CPSCU_Type *) R_CPSCU_BASE)
 #define R_DOC_B          ((R_DOC_B_Type *) R_DOC_B_BASE)
 #define R_AGTW0          ((R_AGTX0_Type *) R_AGTX0_BASE)
 #define R_AGTW1          ((R_AGTX0_Type *) R_AGTX1_BASE)
 #define R_AGTW2          ((R_AGTX0_Type *) R_AGTX2_BASE)
 #define R_AGTW3          ((R_AGTX0_Type *) R_AGTX3_BASE)
 #define R_AGTW4          ((R_AGTX0_Type *) R_AGTX4_BASE)
 #define R_AGTW5          ((R_AGTX0_Type *) R_AGTX5_BASE)
 #define R_AGTW6          ((R_AGTX0_Type *) R_AGTX6_BASE)
 #define R_AGTW7          ((R_AGTX0_Type *) R_AGTX7_BASE)
 #define R_AGTW8          ((R_AGTX0_Type *) R_AGTX8_BASE)
 #define R_AGTW9          ((R_AGTX0_Type *) R_AGTX9_BASE)
 #define R_WDT1           ((R_WDT_Type *) R_WDT1_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */

/* =========================================  End of section using anonymous unions  ========================================= */
 #if defined(__CC_ARM)
  #pragma pop
 #elif defined(__ICCARM__)

/* leave anonymous unions enabled */
 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
 #elif defined(__GNUC__)

/* anonymous unions are enabled by default */
 #elif defined(__TMS470__)

/* anonymous unions are enabled by default */
 #elif defined(__TASKING__)
  #pragma warning restore
 #elif defined(__CSMC__)

/* anonymous unions are enabled by default */
 #endif

/* =========================================================================================================================== */
/* ================                                 Pos/Mask Cluster Section                                  ================ */
/* =========================================================================================================================== */

/** @addtogroup PosMask_clusters
 * @{
 */

/* =========================================================================================================================== */
/* ================                                            CSa                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  MOD  ========================================================== */
 #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
 #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
 #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
 #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
 #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
 #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
/* =========================================================  WCR1  ========================================================== */
 #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
 #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
 #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
 #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
 #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
 #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
 #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
 #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
/* =========================================================  WCR2  ========================================================== */
 #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
 #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
 #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
 #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
 #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
 #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
 #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
 #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
 #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
 #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
 #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
 #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
 #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
 #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
 #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
 #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */

/* =========================================================================================================================== */
/* ================                                            CSb                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
 #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
 #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
 #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
 #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
 #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
 #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
 #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
/* ==========================================================  REC  ========================================================== */
 #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
 #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
 #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
 #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */

/* =========================================================================================================================== */
/* ================                                           SDRAM                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  SDCCR  ========================================================= */
 #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
 #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
 #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
 #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
/* ========================================================  SDCMOD  ========================================================= */
 #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
 #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
/* ========================================================  SDAMOD  ========================================================= */
 #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
 #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
/* ========================================================  SDSELF  ========================================================= */
 #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
 #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
/* ========================================================  SDRFCR  ========================================================= */
 #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
 #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
 #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
 #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
/* ========================================================  SDRFEN  ========================================================= */
 #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
 #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  SDICR  ========================================================= */
 #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
 #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
/* =========================================================  SDIR  ========================================================== */
 #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
 #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
 #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
 #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
 #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
 #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
/* =========================================================  SDADR  ========================================================= */
 #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
 #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
/* =========================================================  SDTR  ========================================================== */
 #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
 #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
 #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
 #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
 #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
 #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
 #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
 #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
 #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
 #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
/* =========================================================  SDMOD  ========================================================= */
 #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
 #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
/* =========================================================  SDSR  ========================================================== */
 #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
 #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
 #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
 #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
 #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
 #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                          BUSERRa                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  ADD  ========================================================== */
 #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
 #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  STAT  ========================================================== */
 #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
 #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
 #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
 #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
/* ==========================================================  RW  =========================================================== */
 #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
 #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                          BTZFERR                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  ADD  ========================================================== */
 #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
 #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  RW  =========================================================== */
 #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
 #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                          BUSERRb                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
 #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
 #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
 #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
 #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
 #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
 #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
 #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
 #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
 #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
 #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
/* ==========================================================  CLR  ========================================================== */
 #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
 #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
 #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
 #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
 #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
 #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
 #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
 #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
 #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
 #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
/* =========================================================  IRQEN  ========================================================= */
 #define R_BUS_BUSERRb_IRQEN_EN_Pos          (0UL)    /*!< EN (Bit 0)                                            */
 #define R_BUS_BUSERRb_IRQEN_EN_Msk          (0x1UL)  /*!< EN (Bitfield-Mask: 0x01)                              */

/* =========================================================================================================================== */
/* ================                                        DMACDTCERR                                         ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
 #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
 #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
/* ==========================================================  CLR  ========================================================== */
 #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
 #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */

/* =========================================================================================================================== */
/* ================                                         BUSSABT0                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  FLBI  ========================================================== */
 #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* ========================================================  MRE0BI  ========================================================= */
 #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  S0BI  ========================================================== */
 #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  S1BI  ========================================================== */
 #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  S2BI  ========================================================== */
 #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  S3BI  ========================================================== */
 #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* ========================================================  STBYSBI  ======================================================== */
 #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  ECBI  ========================================================== */
 #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  EOBI  ========================================================== */
 #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* ========================================================  SPI0BI  ========================================================= */
 #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* ========================================================  SPI1BI  ========================================================= */
 #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  PBBI  ========================================================== */
 #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  PABI  ========================================================== */
 #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  PIBI  ========================================================== */
 #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =========================================================  PSBI  ========================================================== */
 #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =======================================================  CPU0SAHBI  ======================================================= */
 #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */

/* =========================================================================================================================== */
/* ================                                         BUSSABT1                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  FHBI  ========================================================== */
 #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
/* ========================================================  MRC0BI  ========================================================= */
 #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
/* =========================================================  S0BI  ========================================================== */
 #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
/* =========================================================  S1BI  ========================================================== */
 #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */

/* =========================================================================================================================== */
/* ================                                          BMSAERR                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  ADD  ========================================================== */
 #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
 #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
/* ==========================================================  RW  =========================================================== */
 #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
 #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */

/* =========================================================================================================================== */
/* ================                                            OAD                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  BUSOAD  ========================================================= */
 #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
 #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
 #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
 #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
 #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
 #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
/* =======================================================  BUSOADPT  ======================================================== */
 #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
/* ========================================================  MSAOAD  ========================================================= */
 #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
 #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
/* =========================================================  MSAPT  ========================================================= */
 #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                          MBWERR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  STAT  ========================================================== */
 #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
 #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CLR  ========================================================== */
 #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
 #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                           BUSM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
 #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
 #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                           BUSS                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CNT  ========================================================== */
 #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
 #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
 #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */

/* =========================================================================================================================== */
/* ================                                           CFDC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  NCFG  ========================================================== */
 #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
 #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
 #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
 #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
 #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
 #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
 #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
 #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
/* ==========================================================  CTR  ========================================================== */
 #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
 #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
 #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
 #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
 #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
 #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
 #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
 #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
 #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
 #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
 #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
 #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
 #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
 #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
 #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
 #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
 #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
 #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
 #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
 #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
 #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
 #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
 #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
 #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
/* ==========================================================  STS  ========================================================== */
 #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
 #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
 #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
 #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
 #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
 #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
 #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
 #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
 #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
 #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
 #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
 #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
 #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
/* =========================================================  ERFL  ========================================================== */
 #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
 #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
 #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
 #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
 #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
 #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
 #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
 #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
 #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
 #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
 #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
 #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
 #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
 #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
 #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
 #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
 #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */

/* =========================================================================================================================== */
/* ================                                           CFDC2                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  DCFG  ========================================================== */
 #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
 #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
 #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
 #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
 #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
 #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
 #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
 #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
/* =========================================================  FDCFG  ========================================================= */
 #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
 #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
 #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
 #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
 #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
 #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
 #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
 #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
 #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
 #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
 #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
/* =========================================================  FDCTR  ========================================================= */
 #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
 #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
 #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
/* =========================================================  FDSTS  ========================================================= */
 #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
 #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
 #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
 #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
 #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
 #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
 #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
 #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
 #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
/* =========================================================  FDCRC  ========================================================= */
 #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
 #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
 #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
 #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */

/* =========================================================================================================================== */
/* ================                                          CFDGAFL                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
 #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
 #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
 #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
 #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
 #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
 #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
/* ===========================================================  M  =========================================================== */
 #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
 #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
 #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
 #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
 #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
 #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
 #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
 #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
/* ==========================================================  P0  =========================================================== */
 #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
 #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
 #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
 #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
 #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
 #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
 #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
 #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
 #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
/* ==========================================================  P1  =========================================================== */
 #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
 #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */

/* =========================================================================================================================== */
/* ================                                          CFDTHL                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  ACC0  ========================================================== */
 #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
 #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
 #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
 #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
 #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
 #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
/* =========================================================  ACC1  ========================================================== */
 #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
 #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
 #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
 #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */

/* =========================================================================================================================== */
/* ================                                           CFDRF                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
 #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
 #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
 #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
 #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
 #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PTR  ========================================================== */
 #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
 #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
 #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
 #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
/* =========================================================  FDSTS  ========================================================= */
 #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
 #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
 #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
 #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
 #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
 #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  DF  =========================================================== */
 #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
 #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */

/* =========================================================================================================================== */
/* ================                                           CFDCF                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
 #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
 #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
 #define R_CANFD_CFDCF_ID_THLEN_Pos       (29UL)         /*!< THLEN (Bit 29)                                        */
 #define R_CANFD_CFDCF_ID_THLEN_Msk       (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
 #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
 #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PTR  ========================================================== */
 #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
 #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
 #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
 #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
/* =========================================================  FDSTS  ========================================================= */
 #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
 #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
 #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
 #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
 #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
 #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  DF  =========================================================== */
 #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
 #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */

/* =========================================================================================================================== */
/* ================                                           CFDTM                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
 #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
 #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
 #define R_CANFD_CFDTM_ID_THLEN_Pos       (29UL)         /*!< THLEN (Bit 29)                                        */
 #define R_CANFD_CFDTM_ID_THLEN_Msk       (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
 #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
 #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PTR  ========================================================== */
 #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
 #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
 #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
 #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
/* =========================================================  FDCTR  ========================================================= */
 #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
 #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
 #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
 #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
 #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
 #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  DF  =========================================================== */
 #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
 #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */

/* =========================================================================================================================== */
/* ================                                            RM                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  ID  =========================================================== */
 #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
 #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
 #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
 #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
 #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  PTR  ========================================================== */
 #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
 #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
 #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
 #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
/* =========================================================  FDSTS  ========================================================= */
 #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
 #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
 #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
 #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
 #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
 #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  DF  =========================================================== */
 #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
 #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */

/* =========================================================================================================================== */
/* ================                                           CFDRM                                           ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                          ELSEGR                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  BY  =========================================================== */
 #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
 #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
 #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
 #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
 #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
 #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */

/* =========================================================================================================================== */
/* ================                                           ELSR                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  HA  =========================================================== */
 #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
 #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */

/* =========================================================================================================================== */
/* ================                                            SAR                                            ================ */
/* =========================================================================================================================== */

/* ===========================================================  L  =========================================================== */
 #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
 #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
/* ===========================================================  U  =========================================================== */
 #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
 #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
 #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
 #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */

/* =========================================================================================================================== */
/* ================                                          REGION                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  AC  =========================================================== */
 #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos        (3UL)          /*!< PP (Bit 3)                                            */
 #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk        (0x8UL)        /*!< PP (Bitfield-Mask: 0x01)                              */
 #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
 #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
 #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
 #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
 #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
 #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* ===========================================================  S  =========================================================== */
 #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
 #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
/* ===========================================================  E  =========================================================== */
 #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
 #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */

/* =========================================================================================================================== */
/* ================                                           GROUP                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  EN  =========================================================== */
 #define R_MPU_MMPU_GROUP_EN_KEY_Pos             (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_GROUP_EN_KEY_Msk             (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos          (0UL)      /*!< ENABLE (Bit 0)                                        */
 #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk          (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* =========================================================  ENPT  ========================================================== */
 #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
/* ==========================================================  RPT  ========================================================== */
 #define R_MPU_MMPU_GROUP_RPT_KEY_Pos            (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_GROUP_RPT_KEY_Msk            (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos        (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk        (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
/* ========================================================  RPT_SEC  ======================================================== */
 #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                            SP                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  OAD  ========================================================== */
 #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
 #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CTL  ========================================================== */
 #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
 #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
 #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
 #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* ==========================================================  PT  =========================================================== */
 #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
 #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
/* ==========================================================  SA  =========================================================== */
 #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
 #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  EA  =========================================================== */
 #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
 #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */

/* =========================================================================================================================== */
/* ================                                            PIN                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  PmnPFS_BY  ======================================================= */
 #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
/* =======================================================  PmnPFS_HA  ======================================================= */
 #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
 #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
/* ========================================================  PmnPFS  ========================================================= */
 #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
 #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
 #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
 #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
 #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
 #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
 #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
 #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
 #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
 #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */

/* =========================================================================================================================== */
/* ================                                           PORT                                            ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                           PMSAR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  PMSAR  ========================================================= */

/* =========================================================================================================================== */
/* ================                                           RTCCR                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  RTCCR  ========================================================= */
 #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
 #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
 #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
 #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
 #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
 #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
 #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
 #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */

/* =========================================================================================================================== */
/* ================                                            CP                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  RSEC  ========================================================== */
 #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
 #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
 #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  BCNT0  ========================================================= */
 #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
 #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
/* =========================================================  RMIN  ========================================================== */
 #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
 #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
 #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  BCNT1  ========================================================= */
 #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
 #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
/* ==========================================================  RHR  ========================================================== */
 #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
 #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
 #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
 #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
 #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
 #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
/* =========================================================  BCNT2  ========================================================= */
 #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
 #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
/* =========================================================  RDAY  ========================================================== */
 #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
 #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
 #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
 #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
/* =========================================================  BCNT3  ========================================================= */
 #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
 #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
/* =========================================================  RMON  ========================================================== */
 #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
 #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
 #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
 #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */

/* =========================================================================================================================== */
/* ================                                          PIPE_TR                                          ================ */
/* =========================================================================================================================== */

/* ===========================================================  E  =========================================================== */
 #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
 #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
 #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
/* ===========================================================  N  =========================================================== */
 #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
 #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */

/* =========================================================================================================================== */
/* ================                                           CTRL                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  AGTCR  ========================================================= */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
 #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
/* ========================================================  AGTMR1  ========================================================= */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
/* ========================================================  AGTMR2  ========================================================= */
 #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
 #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
/* =====================================================  AGTIOSEL_ALT  ====================================================== */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
/* ========================================================  AGTIOC  ========================================================= */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
 #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
/* ========================================================  AGTISR  ========================================================= */
 #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
/* ========================================================  AGTCMSR  ======================================================== */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
 #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
/* =======================================================  AGTIOSEL  ======================================================== */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
 #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */

/* =========================================================================================================================== */
/* ================                                           AGT16                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  AGT  ========================================================== */
 #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
 #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
/* ========================================================  AGTCMA  ========================================================= */
 #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
 #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
/* ========================================================  AGTCMB  ========================================================= */
 #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
 #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */

/* =========================================================================================================================== */
/* ================                                           AGT32                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  AGT  ========================================================== */
 #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
 #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  AGTCMA  ========================================================= */
 #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
 #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  AGTCMB  ========================================================= */
 #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
 #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */

/** @} */ /* End of group PosMask_clusters */

/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */

/** @addtogroup PosMask_peripherals
 * @{
 */

/* =========================================================================================================================== */
/* ================                                         R_ACMPLP                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  COMPMDR  ======================================================== */
 #define R_ACMPLP_COMPMDR_C1MON_Pos      (7UL)    /*!< C1MON (Bit 7)                                         */
 #define R_ACMPLP_COMPMDR_C1MON_Msk      (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C1VRF_Pos      (6UL)    /*!< C1VRF (Bit 6)                                         */
 #define R_ACMPLP_COMPMDR_C1VRF_Msk      (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C1WDE_Pos      (5UL)    /*!< C1WDE (Bit 5)                                         */
 #define R_ACMPLP_COMPMDR_C1WDE_Msk      (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C1ENB_Pos      (4UL)    /*!< C1ENB (Bit 4)                                         */
 #define R_ACMPLP_COMPMDR_C1ENB_Msk      (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C0MON_Pos      (3UL)    /*!< C0MON (Bit 3)                                         */
 #define R_ACMPLP_COMPMDR_C0MON_Msk      (0x8UL)  /*!< C0MON (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C0WDE_Pos      (1UL)    /*!< C0WDE (Bit 1)                                         */
 #define R_ACMPLP_COMPMDR_C0WDE_Msk      (0x2UL)  /*!< C0WDE (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C0VRF_Pos      (2UL)    /*!< C0VRF (Bit 2)                                         */
 #define R_ACMPLP_COMPMDR_C0VRF_Msk      (0x4UL)  /*!< C0VRF (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPMDR_C0ENB_Pos      (0UL)    /*!< C0ENB (Bit 0)                                         */
 #define R_ACMPLP_COMPMDR_C0ENB_Msk      (0x1UL)  /*!< C0ENB (Bitfield-Mask: 0x01)                           */
/* ========================================================  COMPFIR  ======================================================== */
 #define R_ACMPLP_COMPFIR_C1EDG_Pos      (7UL)    /*!< C1EDG (Bit 7)                                         */
 #define R_ACMPLP_COMPFIR_C1EDG_Msk      (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPFIR_C1EPO_Pos      (6UL)    /*!< C1EPO (Bit 6)                                         */
 #define R_ACMPLP_COMPFIR_C1EPO_Msk      (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPFIR_C1FCK_Pos      (4UL)    /*!< C1FCK (Bit 4)                                         */
 #define R_ACMPLP_COMPFIR_C1FCK_Msk      (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03)                           */
 #define R_ACMPLP_COMPFIR_C0EDG_Pos      (3UL)    /*!< C0EDG (Bit 3)                                         */
 #define R_ACMPLP_COMPFIR_C0EDG_Msk      (0x8UL)  /*!< C0EDG (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPFIR_C0EPO_Pos      (2UL)    /*!< C0EPO (Bit 2)                                         */
 #define R_ACMPLP_COMPFIR_C0EPO_Msk      (0x4UL)  /*!< C0EPO (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPFIR_C0FCK_Pos      (0UL)    /*!< C0FCK (Bit 0)                                         */
 #define R_ACMPLP_COMPFIR_C0FCK_Msk      (0x3UL)  /*!< C0FCK (Bitfield-Mask: 0x03)                           */
/* ========================================================  COMPOCR  ======================================================== */
 #define R_ACMPLP_COMPOCR_SPDMD_Pos      (7UL)    /*!< SPDMD (Bit 7)                                         */
 #define R_ACMPLP_COMPOCR_SPDMD_Msk      (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01)                           */
 #define R_ACMPLP_COMPOCR_C1OP_Pos       (6UL)    /*!< C1OP (Bit 6)                                          */
 #define R_ACMPLP_COMPOCR_C1OP_Msk       (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01)                            */
 #define R_ACMPLP_COMPOCR_C1OE_Pos       (5UL)    /*!< C1OE (Bit 5)                                          */
 #define R_ACMPLP_COMPOCR_C1OE_Msk       (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01)                            */
 #define R_ACMPLP_COMPOCR_C0OP_Pos       (2UL)    /*!< C0OP (Bit 2)                                          */
 #define R_ACMPLP_COMPOCR_C0OP_Msk       (0x4UL)  /*!< C0OP (Bitfield-Mask: 0x01)                            */
 #define R_ACMPLP_COMPOCR_C0OE_Pos       (1UL)    /*!< C0OE (Bit 1)                                          */
 #define R_ACMPLP_COMPOCR_C0OE_Msk       (0x2UL)  /*!< C0OE (Bitfield-Mask: 0x01)                            */
/* =======================================================  COMPSEL0  ======================================================== */
 #define R_ACMPLP_COMPSEL0_IVCMP1_Pos    (4UL)    /*!< IVCMP1 (Bit 4)                                        */
 #define R_ACMPLP_COMPSEL0_IVCMP1_Msk    (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07)                          */
 #define R_ACMPLP_COMPSEL0_IVCMP0_Pos    (0UL)    /*!< IVCMP0 (Bit 0)                                        */
 #define R_ACMPLP_COMPSEL0_IVCMP0_Msk    (0x7UL)  /*!< IVCMP0 (Bitfield-Mask: 0x07)                          */
/* =======================================================  COMPSEL1  ======================================================== */
 #define R_ACMPLP_COMPSEL1_C1VRF2_Pos    (7UL)    /*!< C1VRF2 (Bit 7)                                        */
 #define R_ACMPLP_COMPSEL1_C1VRF2_Msk    (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01)                          */
 #define R_ACMPLP_COMPSEL1_IVREF1_Pos    (4UL)    /*!< IVREF1 (Bit 4)                                        */
 #define R_ACMPLP_COMPSEL1_IVREF1_Msk    (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07)                          */
 #define R_ACMPLP_COMPSEL1_IVREF0_Pos    (0UL)    /*!< IVREF0 (Bit 0)                                        */
 #define R_ACMPLP_COMPSEL1_IVREF0_Msk    (0x7UL)  /*!< IVREF0 (Bitfield-Mask: 0x07)                          */

/* =========================================================================================================================== */
/* ================                                          R_ADC0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  ADCSR  ========================================================= */
 #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
 #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
 #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
 #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
 #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
 #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
 #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
 #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
 #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
 #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
 #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
 #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
/* ========================================================  ADANSA  ========================================================= */
 #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
 #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
/* =========================================================  ADADS  ========================================================= */
 #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
 #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
/* =========================================================  ADADC  ========================================================= */
 #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
 #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
 #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
 #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
/* =========================================================  ADCER  ========================================================= */
 #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
 #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
 #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
 #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
 #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
 #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
 #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
 #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
 #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
 #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
 #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
 #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
/* ========================================================  ADSTRGR  ======================================================== */
 #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
 #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
 #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
 #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
/* ========================================================  ADEXICR  ======================================================== */
 #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
 #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
 #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
 #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
 #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
 #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
 #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
 #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
 #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  ADANSB  ========================================================= */
 #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
 #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
/* ========================================================  ADDBLDR  ======================================================== */
 #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
 #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
/* ========================================================  ADTSDR  ========================================================= */
 #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
 #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
/* ========================================================  ADOCDR  ========================================================= */
 #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
 #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
/* ======================================================  ADRD_RIGHT  ======================================================= */
 #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
 #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
 #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
/* =======================================================  ADRD_LEFT  ======================================================= */
 #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
 #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
 #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
 #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
/* =========================================================  ADDR  ========================================================== */
 #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
 #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
/* ========================================================  ADSHCR  ========================================================= */
 #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
 #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
 #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
 #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
 #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
/* ========================================================  ADDISCR  ======================================================== */
 #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
 #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
 #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
/* ========================================================  ADSHMSR  ======================================================== */
 #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
 #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
/* ========================================================  ADACSR  ========================================================= */
 #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
 #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
/* ========================================================  ADGSPCR  ======================================================== */
 #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
 #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
 #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
 #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
 #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
 #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
/* =========================================================  ADICR  ========================================================= */
 #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
 #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
/* =======================================================  ADDBLDRA  ======================================================== */
 #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
 #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
/* =======================================================  ADDBLDRB  ======================================================== */
 #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
 #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
/* ======================================================  ADHVREFCNT  ======================================================= */
 #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
 #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
 #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
 #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
/* =======================================================  ADWINMON  ======================================================== */
 #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
 #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
 #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
 #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
/* ========================================================  ADCMPCR  ======================================================== */
 #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
 #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
 #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
 #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
 #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
 #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
 #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
/* ======================================================  ADCMPANSER  ======================================================= */
 #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
 #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
 #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADCMPLER  ======================================================== */
 #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
 #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
 #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
/* =======================================================  ADCMPANSR  ======================================================= */
 #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
 #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
/* ========================================================  ADCMPLR  ======================================================== */
 #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
 #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
/* =======================================================  ADCMPDR0  ======================================================== */
 #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
 #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
/* =======================================================  ADCMPDR1  ======================================================== */
 #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
 #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
/* ========================================================  ADCMPSR  ======================================================== */
 #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
 #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
/* =======================================================  ADCMPSER  ======================================================== */
 #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
 #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
 #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
/* =======================================================  ADCMPBNSR  ======================================================= */
 #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
 #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
 #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
/* =======================================================  ADWINLLB  ======================================================== */
 #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
 #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
/* =======================================================  ADWINULB  ======================================================== */
 #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
 #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
/* =======================================================  ADCMPBSR  ======================================================== */
 #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
 #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
/* ========================================================  ADSSTRL  ======================================================== */
 #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
 #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
/* ========================================================  ADSSTRT  ======================================================== */
 #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
 #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
/* ========================================================  ADSSTRO  ======================================================== */
 #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
 #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
/* ========================================================  ADSSTR  ========================================================= */
 #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
 #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
/* ========================================================  ADPGACR  ======================================================== */
 #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
 #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
 #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
 #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
 #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
 #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
 #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
 #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
 #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
 #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
 #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
 #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
 #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
 #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
 #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
 #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
 #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
 #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
 #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
 #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
 #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
/* =========================================================  ADRD  ========================================================== */
 #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
 #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
/* =========================================================  ADRST  ========================================================= */
 #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
 #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
/* ======================================================  VREFAMPCNT  ======================================================= */
 #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
 #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
 #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
 #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
 #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
 #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
 #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
 #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
/* =======================================================  ADCALEXE  ======================================================== */
 #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
 #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
 #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
/* ========================================================  ADANIM  ========================================================= */
 #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
 #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
/* =======================================================  ADPGAGS0  ======================================================== */
 #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
 #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
 #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
 #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
 #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
 #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
 #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
 #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
/* =======================================================  ADPGADCR0  ======================================================= */
 #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
 #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
 #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
 #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
 #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
 #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
 #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
 #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
 #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
/* =========================================================  ADREF  ========================================================= */
 #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
 #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
 #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
 #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
/* ========================================================  ADEXREF  ======================================================== */
 #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
 #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
/* =======================================================  ADAMPOFF  ======================================================== */
 #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
 #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
/* ========================================================  ADTSTPR  ======================================================== */
 #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
 #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
 #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
 #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
/* =======================================================  ADDDACER  ======================================================== */
 #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
 #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
 #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
 #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
 #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
 #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
/* =======================================================  ADEXTSTR  ======================================================== */
 #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
 #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
 #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
 #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
 #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
 #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
 #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
 #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
 #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
 #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
 #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
/* ========================================================  ADTSTRA  ======================================================== */
 #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
 #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
 #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
 #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
 #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
 #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
 #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
 #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
 #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
 #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
 #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
/* ========================================================  ADTSTRB  ======================================================== */
 #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
 #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
/* ========================================================  ADTSTRC  ======================================================== */
 #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
 #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
 #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
 #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
/* ========================================================  ADTSTRD  ======================================================== */
 #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
 #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
/* =======================================================  ADSWTSTR0  ======================================================= */
 #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
 #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADSWTSTR1  ======================================================= */
 #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
 #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADSWTSTR2  ======================================================= */
 #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
 #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
 #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
 #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
 #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
 #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
 #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
 #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
 #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
 #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
 #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
 #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
 #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
 #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
/* ========================================================  ADSWCR  ========================================================= */
 #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
 #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
 #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
 #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
/* ========================================================  ADGSCS  ========================================================= */
 #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
 #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
 #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
 #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
/* =========================================================  ADSER  ========================================================= */
 #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
 #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
/* ========================================================  ADBUF0  ========================================================= */
 #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF1  ========================================================= */
 #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF2  ========================================================= */
 #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF3  ========================================================= */
 #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF4  ========================================================= */
 #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF5  ========================================================= */
 #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF6  ========================================================= */
 #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF7  ========================================================= */
 #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF8  ========================================================= */
 #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF9  ========================================================= */
 #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF10  ======================================================== */
 #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF11  ======================================================== */
 #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF12  ======================================================== */
 #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF13  ======================================================== */
 #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF14  ======================================================== */
 #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUF15  ======================================================== */
 #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
 #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
/* ========================================================  ADBUFEN  ======================================================== */
 #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
 #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
/* =======================================================  ADBUFPTR  ======================================================== */
 #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
 #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
 #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
 #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADPGADBS0  ======================================================= */
 #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
 #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADPGADBS1  ======================================================= */
 #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
 #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
/* =======================================================  ADREFMON  ======================================================== */
 #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
 #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
 #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
 #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */

/* =========================================================================================================================== */
/* ================                                          R_PSCU                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  PSARB  ========================================================= */
 #define R_PSCU_PSARB_PSARB0_Pos     (0UL)          /*!< PSARB0 (Bit 0)                                        */
 #define R_PSCU_PSARB_PSARB0_Msk     (0x1UL)        /*!< PSARB0 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
 #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
 #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
 #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB4_Pos     (4UL)          /*!< PSARB4 (Bit 4)                                        */
 #define R_PSCU_PSARB_PSARB4_Msk     (0x10UL)       /*!< PSARB4 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB5_Pos     (5UL)          /*!< PSARB5 (Bit 5)                                        */
 #define R_PSCU_PSARB_PSARB5_Msk     (0x20UL)       /*!< PSARB5 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
 #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
 #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
 #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
 #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
 #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
 #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
 #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
 #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB17_Pos    (17UL)         /*!< PSARB17 (Bit 17)                                      */
 #define R_PSCU_PSARB_PSARB17_Msk    (0x20000UL)    /*!< PSARB17 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
 #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
 #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
 #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
 #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
 #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
 #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
 #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
 #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
 #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
 #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
 #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
 #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
/* =========================================================  PSARC  ========================================================= */
 #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
 #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
 #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
 #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARC_PSARC4_Pos     (4UL)          /*!< PSARC4 (Bit 4)                                        */
 #define R_PSCU_PSARC_PSARC4_Msk     (0x10UL)       /*!< PSARC4 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
 #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
 #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
 #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
 #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
 #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
 #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
/* =========================================================  PSARD  ========================================================= */
 #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
 #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
 #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
 #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
 #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
 #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
 #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
 #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
 #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
 #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
 #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
 #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
 #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
 #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
 #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
 #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
 #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
 #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARD_PSARD29_Pos    (29UL)         /*!< PSARD29 (Bit 29)                                      */
 #define R_PSCU_PSARD_PSARD29_Msk    (0x20000000UL) /*!< PSARD29 (Bitfield-Mask: 0x01)                         */
/* =========================================================  PSARE  ========================================================= */
 #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
 #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
 #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
 #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
 #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
 #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
 #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
 #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
 #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
 #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
 #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
 #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
 #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
 #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
 #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
 #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
 #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
/* =========================================================  MSSAR  ========================================================= */
 #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
 #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
 #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
 #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
 #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
 #define R_PSCU_MSSAR_MSSAR4_Pos     (4UL)          /*!< MSSAR4 (Bit 4)                                        */
 #define R_PSCU_MSSAR_MSSAR4_Msk     (0x10UL)       /*!< MSSAR4 (Bitfield-Mask: 0x01)                          */
/* =======================================================  CFSAMONA  ======================================================== */
 #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
 #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
/* =======================================================  CFSAMONB  ======================================================== */
 #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
 #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
/* ========================================================  DFSAMON  ======================================================== */
 #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
 #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
/* ========================================================  SSAMONA  ======================================================== */
 #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
 #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
/* ========================================================  SSAMONB  ======================================================== */
 #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
 #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
/* ========================================================  DLMMON  ========================================================= */
 #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
 #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */

/* =========================================================================================================================== */
/* ================                                           R_BUS                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CSRECEN  ======================================================== */
 #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
 #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
 #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
 #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  BUSMABT  ======================================================== */
 #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
 #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
/* =======================================================  BUSDIVBYP  ======================================================= */
 #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
 #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
 #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
 #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
 #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
 #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
/* =======================================================  BUSTHRPUT  ======================================================= */
 #define R_BUS_BUSTHRPUT_DIS_Pos         (0UL)       /*!< DIS (Bit 0)                                           */
 #define R_BUS_BUSTHRPUT_DIS_Msk         (0x1UL)     /*!< DIS (Bitfield-Mask: 0x01)                             */

/* =========================================================================================================================== */
/* ================                                           R_CAC                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CACR0  ========================================================= */
 #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
 #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
/* =========================================================  CACR1  ========================================================= */
 #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
 #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
 #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
 #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
 #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
 #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
 #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
 #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
/* =========================================================  CACR2  ========================================================= */
 #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
 #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
 #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
 #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
 #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
 #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
 #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
 #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
/* =========================================================  CAICR  ========================================================= */
 #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
 #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
 #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
 #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
 #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
 #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
 #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
 #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
 #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
 #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
 #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
 #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
/* =========================================================  CASTR  ========================================================= */
 #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
 #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
 #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
 #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
 #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
 #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
/* ========================================================  CAULVR  ========================================================= */
 #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
 #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
/* ========================================================  CALLVR  ========================================================= */
 #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
 #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
/* ========================================================  CACNTBR  ======================================================== */
 #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
 #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */

/* =========================================================================================================================== */
/* ================                                         R_CANFD0                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  CFDGCFG  ======================================================== */
 #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
 #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
 #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
 #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
 #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
 #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
 #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
 #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
 #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
 #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
 #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
/* ========================================================  CFDGCTR  ======================================================== */
 #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
 #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
 #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
 #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
 #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
 #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
 #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
 #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
 #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
/* ========================================================  CFDGSTS  ======================================================== */
 #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
 #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
 #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
 #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
 #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
/* =======================================================  CFDGERFL  ======================================================== */
 #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
 #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
 #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
 #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
 #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
 #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  CFDGTSC  ======================================================== */
 #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
 #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
/* ======================================================  CFDGAFLECTR  ====================================================== */
 #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
 #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
 #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
 #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
/* ======================================================  CFDGAFLCFG0  ====================================================== */
 #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
 #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
 #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
 #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
/* ========================================================  CFDRMNB  ======================================================== */
 #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
 #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
 #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
 #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
/* =======================================================  CFDRMND0  ======================================================== */
 #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
 #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  CFDRMIEC  ======================================================== */
 #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
 #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  CFDRFCC  ======================================================== */
 #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
 #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
 #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
 #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
 #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
 #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
 #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
 #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
 #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
/* =======================================================  CFDRFSTS  ======================================================== */
 #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
 #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
 #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
 #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
 #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
 #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
/* =======================================================  CFDRFPCTR  ======================================================= */
 #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
 #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
/* ========================================================  CFDCFCC  ======================================================== */
 #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
 #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
 #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
 #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
 #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
 #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
 #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
 #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
 #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
 #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
 #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
 #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
 #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
 #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
 #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
 #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
 #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
 #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
 #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
/* =======================================================  CFDCFSTS  ======================================================== */
 #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
 #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
 #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
 #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
 #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
 #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
 #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
/* =======================================================  CFDCFPCTR  ======================================================= */
 #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
 #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
/* =======================================================  CFDFESTS  ======================================================== */
 #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
 #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
 #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
 #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
/* =======================================================  CFDFFSTS  ======================================================== */
 #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
 #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
 #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
 #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
/* =======================================================  CFDFMSTS  ======================================================== */
 #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
 #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
 #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
 #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
/* =======================================================  CFDRFISTS  ======================================================= */
 #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
 #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x3UL)        /*!< RFXIF (Bitfield-Mask: 0x03)                           */
/* ========================================================  CFDTMC  ========================================================= */
 #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
 #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
 #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
 #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
/* =======================================================  CFDTMSTS  ======================================================== */
 #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
 #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
 #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
 #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
 #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
 #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
/* ======================================================  CFDTMTRSTS  ======================================================= */
 #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
 #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
/* ======================================================  CFDTMTARSTS  ====================================================== */
 #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
 #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
/* ======================================================  CFDTMTCSTS  ======================================================= */
 #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
 #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
/* ======================================================  CFDTMTASTS  ======================================================= */
 #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
 #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
/* =======================================================  CFDTMIEC  ======================================================== */
 #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
 #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
/* =======================================================  CFDTXQCC0  ======================================================= */
 #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
 #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
 #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
 #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
 #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
/* ======================================================  CFDTXQSTS0  ======================================================= */
 #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
 #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
 #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
 #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
 #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
/* ======================================================  CFDTXQPCTR0  ====================================================== */
 #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
 #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
/* =======================================================  CFDTHLCC  ======================================================== */
 #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
 #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
 #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
 #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
 #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
/* =======================================================  CFDTHLSTS  ======================================================= */
 #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
 #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
 #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
 #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
 #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
 #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
/* ======================================================  CFDTHLPCTR  ======================================================= */
 #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
 #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
/* =====================================================  CFDGTINTSTS0  ====================================================== */
 #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
 #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
 #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
 #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
 #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
 #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
 #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
 #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
/* ======================================================  CFDGTSTCFG  ======================================================= */
 #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
 #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
/* ======================================================  CFDGTSTCTR  ======================================================= */
 #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
 #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
/* =======================================================  CFDGFDCFG  ======================================================= */
 #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
 #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
 #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
/* =======================================================  CFDGLOCKK  ======================================================= */
 #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
 #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
/* =====================================================  CFDGAFLIGNENT  ===================================================== */
 #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
 #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
/* =====================================================  CFDGAFLIGNCTR  ===================================================== */
 #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
 #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
/* =======================================================  CFDCDTCT  ======================================================== */
 #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
 #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
 #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
 #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
 #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
/* =======================================================  CFDCDTSTS  ======================================================= */
 #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
 #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
 #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
 #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
 #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
 #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
/* =======================================================  CFDGRSTC  ======================================================== */
 #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
 #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
 #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
/* =======================================================  CFDRPGACC  ======================================================= */
 #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
 #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */

/* =========================================================================================================================== */
/* ================                                           R_CRC                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  CRCCR0  ========================================================= */
 #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
 #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
 #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
 #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
 #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
 #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
/* ========================================================  CRCCR1  ========================================================= */
 #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
 #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
 #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
 #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
/* ========================================================  CRCDIR  ========================================================= */
 #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
 #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  CRCDIR_BY  ======================================================= */
 #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
 #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
/* ========================================================  CRCDOR  ========================================================= */
 #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
 #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  CRCDOR_HA  ======================================================= */
 #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
 #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
/* =======================================================  CRCDOR_BY  ======================================================= */
 #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
 #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
/* ========================================================  CRCSAR  ========================================================= */
 #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
 #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */

/* =========================================================================================================================== */
/* ================                                          R_CTSU2                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  CTSUCRA  ======================================================== */
 #define R_CTSU2_CTSUCRA_STRT_Pos      (0UL)          /*!< STRT (Bit 0)                                          */
 #define R_CTSU2_CTSUCRA_STRT_Msk      (0x1UL)        /*!< STRT (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUCRA_CAP_Pos       (1UL)          /*!< CAP (Bit 1)                                           */
 #define R_CTSU2_CTSUCRA_CAP_Msk       (0x2UL)        /*!< CAP (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_SNZ_Pos       (2UL)          /*!< SNZ (Bit 2)                                           */
 #define R_CTSU2_CTSUCRA_SNZ_Msk       (0x4UL)        /*!< SNZ (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_CFCON_Pos     (3UL)          /*!< CFCON (Bit 3)                                         */
 #define R_CTSU2_CTSUCRA_CFCON_Msk     (0x8UL)        /*!< CFCON (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUCRA_INIT_Pos      (4UL)          /*!< INIT (Bit 4)                                          */
 #define R_CTSU2_CTSUCRA_INIT_Msk      (0x10UL)       /*!< INIT (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUCRA_PUMPON_Pos    (5UL)          /*!< PUMPON (Bit 5)                                        */
 #define R_CTSU2_CTSUCRA_PUMPON_Msk    (0x20UL)       /*!< PUMPON (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_TXVSEL_Pos    (6UL)          /*!< TXVSEL (Bit 6)                                        */
 #define R_CTSU2_CTSUCRA_TXVSEL_Msk    (0xc0UL)       /*!< TXVSEL (Bitfield-Mask: 0x03)                          */
 #define R_CTSU2_CTSUCRA_PON_Pos       (8UL)          /*!< PON (Bit 8)                                           */
 #define R_CTSU2_CTSUCRA_PON_Msk       (0x100UL)      /*!< PON (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_CSW_Pos       (9UL)          /*!< CSW (Bit 9)                                           */
 #define R_CTSU2_CTSUCRA_CSW_Msk       (0x200UL)      /*!< CSW (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_ATUNE0_Pos    (10UL)         /*!< ATUNE0 (Bit 10)                                       */
 #define R_CTSU2_CTSUCRA_ATUNE0_Msk    (0x400UL)      /*!< ATUNE0 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_ATUNE1_Pos    (11UL)         /*!< ATUNE1 (Bit 11)                                       */
 #define R_CTSU2_CTSUCRA_ATUNE1_Msk    (0x800UL)      /*!< ATUNE1 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_CLK_Pos       (12UL)         /*!< CLK (Bit 12)                                          */
 #define R_CTSU2_CTSUCRA_CLK_Msk       (0x3000UL)     /*!< CLK (Bitfield-Mask: 0x03)                             */
 #define R_CTSU2_CTSUCRA_MD0_Pos       (14UL)         /*!< MD0 (Bit 14)                                          */
 #define R_CTSU2_CTSUCRA_MD0_Msk       (0x4000UL)     /*!< MD0 (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_MD1_Pos       (15UL)         /*!< MD1 (Bit 15)                                          */
 #define R_CTSU2_CTSUCRA_MD1_Msk       (0x8000UL)     /*!< MD1 (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_MD2_Pos       (16UL)         /*!< MD2 (Bit 16)                                          */
 #define R_CTSU2_CTSUCRA_MD2_Msk       (0x10000UL)    /*!< MD2 (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCRA_ATUNE2_Pos    (17UL)         /*!< ATUNE2 (Bit 17)                                       */
 #define R_CTSU2_CTSUCRA_ATUNE2_Msk    (0x20000UL)    /*!< ATUNE2 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_LOAD_Pos      (18UL)         /*!< LOAD (Bit 18)                                         */
 #define R_CTSU2_CTSUCRA_LOAD_Msk      (0xc0000UL)    /*!< LOAD (Bitfield-Mask: 0x03)                            */
 #define R_CTSU2_CTSUCRA_POSEL_Pos     (20UL)         /*!< POSEL (Bit 20)                                        */
 #define R_CTSU2_CTSUCRA_POSEL_Msk     (0x300000UL)   /*!< POSEL (Bitfield-Mask: 0x03)                           */
 #define R_CTSU2_CTSUCRA_SDPSEL_Pos    (22UL)         /*!< SDPSEL (Bit 22)                                       */
 #define R_CTSU2_CTSUCRA_SDPSEL_Msk    (0x400000UL)   /*!< SDPSEL (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_PCSEL_Pos     (23UL)         /*!< PCSEL (Bit 23)                                        */
 #define R_CTSU2_CTSUCRA_PCSEL_Msk     (0x800000UL)   /*!< PCSEL (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUCRA_STCLK_Pos     (24UL)         /*!< STCLK (Bit 24)                                        */
 #define R_CTSU2_CTSUCRA_STCLK_Msk     (0x3f000000UL) /*!< STCLK (Bitfield-Mask: 0x3f)                           */
 #define R_CTSU2_CTSUCRA_DCMODE_Pos    (30UL)         /*!< DCMODE (Bit 30)                                       */
 #define R_CTSU2_CTSUCRA_DCMODE_Msk    (0x40000000UL) /*!< DCMODE (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCRA_DCBACK_Pos    (31UL)         /*!< DCBACK (Bit 31)                                       */
 #define R_CTSU2_CTSUCRA_DCBACK_Msk    (0x80000000UL) /*!< DCBACK (Bitfield-Mask: 0x01)                          */
/* =======================================================  CTSUCRAL  ======================================================== */
/* ========================================================  CTSUCR0  ======================================================== */
/* ========================================================  CTSUCR1  ======================================================== */
/* =======================================================  CTSUCRAH  ======================================================== */
/* ========================================================  CTSUCR2  ======================================================== */
/* ========================================================  CTSUCR3  ======================================================== */
/* ========================================================  CTSUCRB  ======================================================== */
 #define R_CTSU2_CTSUCRB_PRRATIO_Pos    (0UL)          /*!< PRRATIO (Bit 0)                                       */
 #define R_CTSU2_CTSUCRB_PRRATIO_Msk    (0xfUL)        /*!< PRRATIO (Bitfield-Mask: 0x0f)                         */
 #define R_CTSU2_CTSUCRB_PRMODE_Pos     (4UL)          /*!< PRMODE (Bit 4)                                        */
 #define R_CTSU2_CTSUCRB_PRMODE_Msk     (0x30UL)       /*!< PRMODE (Bitfield-Mask: 0x03)                          */
 #define R_CTSU2_CTSUCRB_SOFF_Pos       (6UL)          /*!< SOFF (Bit 6)                                          */
 #define R_CTSU2_CTSUCRB_SOFF_Msk       (0x40UL)       /*!< SOFF (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUCRB_PROFF_Pos      (7UL)          /*!< PROFF (Bit 7)                                         */
 #define R_CTSU2_CTSUCRB_PROFF_Msk      (0x80UL)       /*!< PROFF (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUCRB_SST_Pos        (8UL)          /*!< SST (Bit 8)                                           */
 #define R_CTSU2_CTSUCRB_SST_Msk        (0xff00UL)     /*!< SST (Bitfield-Mask: 0xff)                             */
 #define R_CTSU2_CTSUCRB_SSMOD_Pos      (24UL)         /*!< SSMOD (Bit 24)                                        */
 #define R_CTSU2_CTSUCRB_SSMOD_Msk      (0x7000000UL)  /*!< SSMOD (Bitfield-Mask: 0x07)                           */
 #define R_CTSU2_CTSUCRB_SSCNT_Pos      (28UL)         /*!< SSCNT (Bit 28)                                        */
 #define R_CTSU2_CTSUCRB_SSCNT_Msk      (0x30000000UL) /*!< SSCNT (Bitfield-Mask: 0x03)                           */
/* =======================================================  CTSUCRBL  ======================================================== */
/* =======================================================  CTSUSDPRS  ======================================================= */
/* ========================================================  CTSUSST  ======================================================== */
/* =======================================================  CTSUCRBH  ======================================================== */
/* =======================================================  CTSUDCLKC  ======================================================= */
/* ========================================================  CTSUMCH  ======================================================== */
 #define R_CTSU2_CTSUMCH_MCH0_Pos    (0UL)       /*!< MCH0 (Bit 0)                                          */
 #define R_CTSU2_CTSUMCH_MCH0_Msk    (0x3fUL)    /*!< MCH0 (Bitfield-Mask: 0x3f)                            */
 #define R_CTSU2_CTSUMCH_MCH1_Pos    (8UL)       /*!< MCH1 (Bit 8)                                          */
 #define R_CTSU2_CTSUMCH_MCH1_Msk    (0x3f00UL)  /*!< MCH1 (Bitfield-Mask: 0x3f)                            */
 #define R_CTSU2_CTSUMCH_MCA0_Pos    (16UL)      /*!< MCA0 (Bit 16)                                         */
 #define R_CTSU2_CTSUMCH_MCA0_Msk    (0x10000UL) /*!< MCA0 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUMCH_MCA1_Pos    (17UL)      /*!< MCA1 (Bit 17)                                         */
 #define R_CTSU2_CTSUMCH_MCA1_Msk    (0x20000UL) /*!< MCA1 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUMCH_MCA2_Pos    (18UL)      /*!< MCA2 (Bit 18)                                         */
 #define R_CTSU2_CTSUMCH_MCA2_Msk    (0x40000UL) /*!< MCA2 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUMCH_MCA3_Pos    (19UL)      /*!< MCA3 (Bit 19)                                         */
 #define R_CTSU2_CTSUMCH_MCA3_Msk    (0x80000UL) /*!< MCA3 (Bitfield-Mask: 0x01)                            */
/* =======================================================  CTSUMCHL  ======================================================== */
/* =======================================================  CTSUMCH0  ======================================================== */
/* =======================================================  CTSUMCH1  ======================================================== */
/* =======================================================  CTSUMCHH  ======================================================== */
/* =======================================================  CTSUMFAF  ======================================================== */
/* =======================================================  CTSUCHACA  ======================================================= */
 #define R_CTSU2_CTSUCHACA_CHAC00_Pos    (0UL)          /*!< CHAC00 (Bit 0)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC00_Msk    (0x1UL)        /*!< CHAC00 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC01_Pos    (1UL)          /*!< CHAC01 (Bit 1)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC01_Msk    (0x2UL)        /*!< CHAC01 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC02_Pos    (2UL)          /*!< CHAC02 (Bit 2)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC02_Msk    (0x4UL)        /*!< CHAC02 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC03_Pos    (3UL)          /*!< CHAC03 (Bit 3)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC03_Msk    (0x8UL)        /*!< CHAC03 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC04_Pos    (4UL)          /*!< CHAC04 (Bit 4)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC04_Msk    (0x10UL)       /*!< CHAC04 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC05_Pos    (5UL)          /*!< CHAC05 (Bit 5)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC05_Msk    (0x20UL)       /*!< CHAC05 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC06_Pos    (6UL)          /*!< CHAC06 (Bit 6)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC06_Msk    (0x40UL)       /*!< CHAC06 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC07_Pos    (7UL)          /*!< CHAC07 (Bit 7)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC07_Msk    (0x80UL)       /*!< CHAC07 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC08_Pos    (8UL)          /*!< CHAC08 (Bit 8)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC08_Msk    (0x100UL)      /*!< CHAC08 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC09_Pos    (9UL)          /*!< CHAC09 (Bit 9)                                        */
 #define R_CTSU2_CTSUCHACA_CHAC09_Msk    (0x200UL)      /*!< CHAC09 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC10_Pos    (10UL)         /*!< CHAC10 (Bit 10)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC10_Msk    (0x400UL)      /*!< CHAC10 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC11_Pos    (11UL)         /*!< CHAC11 (Bit 11)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC11_Msk    (0x800UL)      /*!< CHAC11 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC12_Pos    (12UL)         /*!< CHAC12 (Bit 12)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC12_Msk    (0x1000UL)     /*!< CHAC12 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC13_Pos    (13UL)         /*!< CHAC13 (Bit 13)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC13_Msk    (0x2000UL)     /*!< CHAC13 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC14_Pos    (14UL)         /*!< CHAC14 (Bit 14)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC14_Msk    (0x4000UL)     /*!< CHAC14 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC15_Pos    (15UL)         /*!< CHAC15 (Bit 15)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC15_Msk    (0x8000UL)     /*!< CHAC15 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC16_Pos    (16UL)         /*!< CHAC16 (Bit 16)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC16_Msk    (0x10000UL)    /*!< CHAC16 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC17_Pos    (17UL)         /*!< CHAC17 (Bit 17)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC17_Msk    (0x20000UL)    /*!< CHAC17 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC18_Pos    (18UL)         /*!< CHAC18 (Bit 18)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC18_Msk    (0x40000UL)    /*!< CHAC18 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC19_Pos    (19UL)         /*!< CHAC19 (Bit 19)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC19_Msk    (0x80000UL)    /*!< CHAC19 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC20_Pos    (20UL)         /*!< CHAC20 (Bit 20)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC20_Msk    (0x100000UL)   /*!< CHAC20 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC21_Pos    (21UL)         /*!< CHAC21 (Bit 21)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC21_Msk    (0x200000UL)   /*!< CHAC21 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC22_Pos    (22UL)         /*!< CHAC22 (Bit 22)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC22_Msk    (0x400000UL)   /*!< CHAC22 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC23_Pos    (23UL)         /*!< CHAC23 (Bit 23)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC23_Msk    (0x800000UL)   /*!< CHAC23 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC24_Pos    (24UL)         /*!< CHAC24 (Bit 24)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC24_Msk    (0x1000000UL)  /*!< CHAC24 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC25_Pos    (25UL)         /*!< CHAC25 (Bit 25)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC25_Msk    (0x2000000UL)  /*!< CHAC25 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC26_Pos    (26UL)         /*!< CHAC26 (Bit 26)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC26_Msk    (0x4000000UL)  /*!< CHAC26 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC27_Pos    (27UL)         /*!< CHAC27 (Bit 27)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC27_Msk    (0x8000000UL)  /*!< CHAC27 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC28_Pos    (28UL)         /*!< CHAC28 (Bit 28)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC28_Msk    (0x10000000UL) /*!< CHAC28 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC29_Pos    (29UL)         /*!< CHAC29 (Bit 29)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC29_Msk    (0x20000000UL) /*!< CHAC29 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC30_Pos    (30UL)         /*!< CHAC30 (Bit 30)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC30_Msk    (0x40000000UL) /*!< CHAC30 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACA_CHAC31_Pos    (31UL)         /*!< CHAC31 (Bit 31)                                       */
 #define R_CTSU2_CTSUCHACA_CHAC31_Msk    (0x80000000UL) /*!< CHAC31 (Bitfield-Mask: 0x01)                          */
/* ======================================================  CTSUCHACAL  ======================================================= */
/* =======================================================  CTSUCHAC0  ======================================================= */
/* =======================================================  CTSUCHAC1  ======================================================= */
/* ======================================================  CTSUCHACAH  ======================================================= */
/* =======================================================  CTSUCHAC2  ======================================================= */
/* =======================================================  CTSUCHAC3  ======================================================= */
/* =======================================================  CTSUCHACB  ======================================================= */
 #define R_CTSU2_CTSUCHACB_CHAC32_Pos      (0UL)          /*!< CHAC32 (Bit 0)                                        */
 #define R_CTSU2_CTSUCHACB_CHAC32_Msk      (0x1UL)        /*!< CHAC32 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACB_CHAC33_Pos      (1UL)          /*!< CHAC33 (Bit 1)                                        */
 #define R_CTSU2_CTSUCHACB_CHAC33_Msk      (0x2UL)        /*!< CHAC33 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACB_CHAC34_Pos      (2UL)          /*!< CHAC34 (Bit 2)                                        */
 #define R_CTSU2_CTSUCHACB_CHAC34_Msk      (0x4UL)        /*!< CHAC34 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCHACB_CHAC35_Pos      (3UL)          /*!< CHAC35 (Bit 3)                                        */
 #define R_CTSU2_CTSUCHACB_CHAC35_Msk      (0x8UL)        /*!< CHAC35 (Bitfield-Mask: 0x01)                          */
/* ======================================================  CTSUCHACBL  ======================================================= */
/* =======================================================  CTSUCHAC4  ======================================================= */
/* ======================================================  CTSUCHTRCA  ======================================================= */
 #define R_CTSU2_CTSUCHTRCA_CHTRC_Pos      (0UL)          /*!< CHTRC (Bit 0)                                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC_Msk      (0x1UL)        /*!< CHTRC (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUCHTRCA_CHTRC01_Pos    (1UL)          /*!< CHTRC01 (Bit 1)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC01_Msk    (0x2UL)        /*!< CHTRC01 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC02_Pos    (2UL)          /*!< CHTRC02 (Bit 2)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC02_Msk    (0x4UL)        /*!< CHTRC02 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC03_Pos    (3UL)          /*!< CHTRC03 (Bit 3)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC03_Msk    (0x8UL)        /*!< CHTRC03 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC04_Pos    (4UL)          /*!< CHTRC04 (Bit 4)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC04_Msk    (0x10UL)       /*!< CHTRC04 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC05_Pos    (5UL)          /*!< CHTRC05 (Bit 5)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC05_Msk    (0x20UL)       /*!< CHTRC05 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC06_Pos    (6UL)          /*!< CHTRC06 (Bit 6)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC06_Msk    (0x40UL)       /*!< CHTRC06 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC07_Pos    (7UL)          /*!< CHTRC07 (Bit 7)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC07_Msk    (0x80UL)       /*!< CHTRC07 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC08_Pos    (8UL)          /*!< CHTRC08 (Bit 8)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC08_Msk    (0x100UL)      /*!< CHTRC08 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC09_Pos    (9UL)          /*!< CHTRC09 (Bit 9)                                       */
 #define R_CTSU2_CTSUCHTRCA_CHTRC09_Msk    (0x200UL)      /*!< CHTRC09 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC10_Pos    (10UL)         /*!< CHTRC10 (Bit 10)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC10_Msk    (0x400UL)      /*!< CHTRC10 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC11_Pos    (11UL)         /*!< CHTRC11 (Bit 11)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC11_Msk    (0x800UL)      /*!< CHTRC11 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC12_Pos    (12UL)         /*!< CHTRC12 (Bit 12)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC12_Msk    (0x1000UL)     /*!< CHTRC12 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC13_Pos    (13UL)         /*!< CHTRC13 (Bit 13)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC13_Msk    (0x2000UL)     /*!< CHTRC13 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC14_Pos    (14UL)         /*!< CHTRC14 (Bit 14)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC14_Msk    (0x4000UL)     /*!< CHTRC14 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC15_Pos    (15UL)         /*!< CHTRC15 (Bit 15)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC15_Msk    (0x8000UL)     /*!< CHTRC15 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC16_Pos    (16UL)         /*!< CHTRC16 (Bit 16)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC16_Msk    (0x10000UL)    /*!< CHTRC16 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC17_Pos    (17UL)         /*!< CHTRC17 (Bit 17)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC17_Msk    (0x20000UL)    /*!< CHTRC17 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC18_Pos    (18UL)         /*!< CHTRC18 (Bit 18)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC18_Msk    (0x40000UL)    /*!< CHTRC18 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC19_Pos    (19UL)         /*!< CHTRC19 (Bit 19)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC19_Msk    (0x80000UL)    /*!< CHTRC19 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC20_Pos    (20UL)         /*!< CHTRC20 (Bit 20)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC20_Msk    (0x100000UL)   /*!< CHTRC20 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC21_Pos    (21UL)         /*!< CHTRC21 (Bit 21)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC21_Msk    (0x200000UL)   /*!< CHTRC21 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC22_Pos    (22UL)         /*!< CHTRC22 (Bit 22)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC22_Msk    (0x400000UL)   /*!< CHTRC22 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC23_Pos    (23UL)         /*!< CHTRC23 (Bit 23)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC23_Msk    (0x800000UL)   /*!< CHTRC23 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC24_Pos    (24UL)         /*!< CHTRC24 (Bit 24)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC24_Msk    (0x1000000UL)  /*!< CHTRC24 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC25_Pos    (25UL)         /*!< CHTRC25 (Bit 25)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC25_Msk    (0x2000000UL)  /*!< CHTRC25 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC26_Pos    (26UL)         /*!< CHTRC26 (Bit 26)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC26_Msk    (0x4000000UL)  /*!< CHTRC26 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC27_Pos    (27UL)         /*!< CHTRC27 (Bit 27)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC27_Msk    (0x8000000UL)  /*!< CHTRC27 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC28_Pos    (28UL)         /*!< CHTRC28 (Bit 28)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC28_Msk    (0x10000000UL) /*!< CHTRC28 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC29_Pos    (29UL)         /*!< CHTRC29 (Bit 29)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC29_Msk    (0x20000000UL) /*!< CHTRC29 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC30_Pos    (30UL)         /*!< CHTRC30 (Bit 30)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC30_Msk    (0x40000000UL) /*!< CHTRC30 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCA_CHTRC31_Pos    (31UL)         /*!< CHTRC31 (Bit 31)                                      */
 #define R_CTSU2_CTSUCHTRCA_CHTRC31_Msk    (0x80000000UL) /*!< CHTRC31 (Bitfield-Mask: 0x01)                         */
/* ======================================================  CTSUCHTRCAL  ====================================================== */
/* ======================================================  CTSUCHTRC0  ======================================================= */
/* ======================================================  CTSUCHTRC1  ======================================================= */
/* ======================================================  CTSUCHTRCAH  ====================================================== */
/* ======================================================  CTSUCHTRC2  ======================================================= */
/* ======================================================  CTSUCHTRC3  ======================================================= */
/* ======================================================  CTSUCHTRCB  ======================================================= */
 #define R_CTSU2_CTSUCHTRCB_CHTRC32_Pos    (0UL)        /*!< CHTRC32 (Bit 0)                                       */
 #define R_CTSU2_CTSUCHTRCB_CHTRC32_Msk    (0x1UL)      /*!< CHTRC32 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCB_CHTRC33_Pos    (1UL)        /*!< CHTRC33 (Bit 1)                                       */
 #define R_CTSU2_CTSUCHTRCB_CHTRC33_Msk    (0x2UL)      /*!< CHTRC33 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCB_CHTRC34_Pos    (2UL)        /*!< CHTRC34 (Bit 2)                                       */
 #define R_CTSU2_CTSUCHTRCB_CHTRC34_Msk    (0x4UL)      /*!< CHTRC34 (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCHTRCB_CHTRC35_Pos    (3UL)        /*!< CHTRC35 (Bit 3)                                       */
 #define R_CTSU2_CTSUCHTRCB_CHTRC35_Msk    (0x8UL)      /*!< CHTRC35 (Bitfield-Mask: 0x01)                         */
/* ======================================================  CTSUCHTRCBL  ====================================================== */
/* ======================================================  CTSUCHTRC4  ======================================================= */
/* ========================================================  CTSUSR  ========================================================= */
 #define R_CTSU2_CTSUSR_MFC_Pos            (0UL)        /*!< MFC (Bit 0)                                           */
 #define R_CTSU2_CTSUSR_MFC_Msk            (0x3UL)      /*!< MFC (Bitfield-Mask: 0x03)                             */
 #define R_CTSU2_CTSUSR_ICOMPRST_Pos       (5UL)        /*!< ICOMPRST (Bit 5)                                      */
 #define R_CTSU2_CTSUSR_ICOMPRST_Msk       (0x20UL)     /*!< ICOMPRST (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_CTSUSR_ICOMP1_Pos         (6UL)        /*!< ICOMP1 (Bit 6)                                        */
 #define R_CTSU2_CTSUSR_ICOMP1_Msk         (0x40UL)     /*!< ICOMP1 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUSR_ICOMP0_Pos         (7UL)        /*!< ICOMP0 (Bit 7)                                        */
 #define R_CTSU2_CTSUSR_ICOMP0_Msk         (0x80UL)     /*!< ICOMP0 (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUSR_STC_Pos            (8UL)        /*!< STC (Bit 8)                                           */
 #define R_CTSU2_CTSUSR_STC_Msk            (0x700UL)    /*!< STC (Bitfield-Mask: 0x07)                             */
 #define R_CTSU2_CTSUSR_DTSR_Pos           (12UL)       /*!< DTSR (Bit 12)                                         */
 #define R_CTSU2_CTSUSR_DTSR_Msk           (0x1000UL)   /*!< DTSR (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUSR_SENSOVF_Pos        (13UL)       /*!< SENSOVF (Bit 13)                                      */
 #define R_CTSU2_CTSUSR_SENSOVF_Msk        (0x2000UL)   /*!< SENSOVF (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUSR_SUOVF_Pos          (14UL)       /*!< SUOVF (Bit 14)                                        */
 #define R_CTSU2_CTSUSR_SUOVF_Msk          (0x4000UL)   /*!< SUOVF (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUSR_PS_Pos             (15UL)       /*!< PS (Bit 15)                                           */
 #define R_CTSU2_CTSUSR_PS_Msk             (0x8000UL)   /*!< PS (Bitfield-Mask: 0x01)                              */
 #define R_CTSU2_CTSUSR_CFCRDCH_Pos        (16UL)       /*!< CFCRDCH (Bit 16)                                      */
 #define R_CTSU2_CTSUSR_CFCRDCH_Msk        (0x3f0000UL) /*!< CFCRDCH (Bitfield-Mask: 0x3f)                         */
/* ========================================================  CTSUSRL  ======================================================== */
/* ========================================================  CTSUSR0  ======================================================== */
/* ========================================================  CTSUST  ========================================================= */
/* ========================================================  CTSUSRH  ======================================================== */
/* ========================================================  CTSUSR2  ======================================================== */
/* ========================================================  CTSUSO  ========================================================= */
 #define R_CTSU2_CTSUSO_SO_Pos                  (0UL)          /*!< SO (Bit 0)                                            */
 #define R_CTSU2_CTSUSO_SO_Msk                  (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
 #define R_CTSU2_CTSUSO_SNUM_Pos                (10UL)         /*!< SNUM (Bit 10)                                         */
 #define R_CTSU2_CTSUSO_SNUM_Msk                (0x3fc00UL)    /*!< SNUM (Bitfield-Mask: 0xff)                            */
 #define R_CTSU2_CTSUSO_SSDIV_Pos               (20UL)         /*!< SSDIV (Bit 20)                                        */
 #define R_CTSU2_CTSUSO_SSDIV_Msk               (0xf00000UL)   /*!< SSDIV (Bitfield-Mask: 0x0f)                           */
 #define R_CTSU2_CTSUSO_SDPA_Pos                (24UL)         /*!< SDPA (Bit 24)                                         */
 #define R_CTSU2_CTSUSO_SDPA_Msk                (0xff000000UL) /*!< SDPA (Bitfield-Mask: 0xff)                            */
/* ========================================================  CTSUSO0  ======================================================== */
/* ========================================================  CTSUSO1  ======================================================== */
/* =======================================================  CTSUSCNT  ======================================================== */
 #define R_CTSU2_CTSUSCNT_SENSCNT_Pos           (0UL)          /*!< SENSCNT (Bit 0)                                       */
 #define R_CTSU2_CTSUSCNT_SENSCNT_Msk           (0xffffUL)     /*!< SENSCNT (Bitfield-Mask: 0xffff)                       */
 #define R_CTSU2_CTSUSCNT_SUCKCNT_Pos           (16UL)         /*!< SUCKCNT (Bit 16)                                      */
 #define R_CTSU2_CTSUSCNT_SUCKCNT_Msk           (0xffff0000UL) /*!< SUCKCNT (Bitfield-Mask: 0xffff)                       */
/* ========================================================  CTSUSC  ========================================================= */
/* =======================================================  CTSUCALIB  ======================================================= */
 #define R_CTSU2_CTSUCALIB_TSOD_Pos             (2UL)          /*!< TSOD (Bit 2)                                          */
 #define R_CTSU2_CTSUCALIB_TSOD_Msk             (0x4UL)        /*!< TSOD (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUCALIB_DRV_Pos              (3UL)          /*!< DRV (Bit 3)                                           */
 #define R_CTSU2_CTSUCALIB_DRV_Msk              (0x8UL)        /*!< DRV (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCALIB_CLKSEL_Pos           (4UL)          /*!< CLKSEL (Bit 4)                                        */
 #define R_CTSU2_CTSUCALIB_CLKSEL_Msk           (0x30UL)       /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
 #define R_CTSU2_CTSUCALIB_SUCLKEN_Pos          (6UL)          /*!< SUCLKEN (Bit 6)                                       */
 #define R_CTSU2_CTSUCALIB_SUCLKEN_Msk          (0x40UL)       /*!< SUCLKEN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCALIB_TSOC_Pos             (7UL)          /*!< TSOC (Bit 7)                                          */
 #define R_CTSU2_CTSUCALIB_TSOC_Msk             (0x80UL)       /*!< TSOC (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUCALIB_CNTRDSEL_Pos         (8UL)          /*!< CNTRDSEL (Bit 8)                                      */
 #define R_CTSU2_CTSUCALIB_CNTRDSEL_Msk         (0x100UL)      /*!< CNTRDSEL (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_CTSUCALIB_IOC_Pos              (9UL)          /*!< IOC (Bit 9)                                           */
 #define R_CTSU2_CTSUCALIB_IOC_Msk              (0x200UL)      /*!< IOC (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUCALIB_CFCRDMD_Pos          (10UL)         /*!< CFCRDMD (Bit 10)                                      */
 #define R_CTSU2_CTSUCALIB_CFCRDMD_Msk          (0x400UL)      /*!< CFCRDMD (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCALIB_DCOFF_Pos            (11UL)         /*!< DCOFF (Bit 11)                                        */
 #define R_CTSU2_CTSUCALIB_DCOFF_Msk            (0x800UL)      /*!< DCOFF (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUCALIB_IOCSEL_Pos           (12UL)         /*!< IOCSEL (Bit 12)                                       */
 #define R_CTSU2_CTSUCALIB_IOCSEL_Msk           (0x1000UL)     /*!< IOCSEL (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCALIB_CFCSEL_Pos           (16UL)         /*!< CFCSEL (Bit 16)                                       */
 #define R_CTSU2_CTSUCALIB_CFCSEL_Msk           (0x3f0000UL)   /*!< CFCSEL (Bitfield-Mask: 0x3f)                          */
 #define R_CTSU2_CTSUCALIB_CFCMODE_Pos          (22UL)         /*!< CFCMODE (Bit 22)                                      */
 #define R_CTSU2_CTSUCALIB_CFCMODE_Msk          (0x400000UL)   /*!< CFCMODE (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCALIB_DACMSEL_Pos          (24UL)         /*!< DACMSEL (Bit 24)                                      */
 #define R_CTSU2_CTSUCALIB_DACMSEL_Msk          (0x1000000UL)  /*!< DACMSEL (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCALIB_DACCARRY_Pos         (25UL)         /*!< DACCARRY (Bit 25)                                     */
 #define R_CTSU2_CTSUCALIB_DACCARRY_Msk         (0x2000000UL)  /*!< DACCARRY (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_CTSUCALIB_SUMSEL_Pos           (26UL)         /*!< SUMSEL (Bit 26)                                       */
 #define R_CTSU2_CTSUCALIB_SUMSEL_Msk           (0x4000000UL)  /*!< SUMSEL (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCALIB_SUCARRY_Pos          (27UL)         /*!< SUCARRY (Bit 27)                                      */
 #define R_CTSU2_CTSUCALIB_SUCARRY_Msk          (0x8000000UL)  /*!< SUCARRY (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUCALIB_DACCLK_Pos           (28UL)         /*!< DACCLK (Bit 28)                                       */
 #define R_CTSU2_CTSUCALIB_DACCLK_Msk           (0x10000000UL) /*!< DACCLK (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCALIB_CCOCLK_Pos           (29UL)         /*!< CCOCLK (Bit 29)                                       */
 #define R_CTSU2_CTSUCALIB_CCOCLK_Msk           (0x20000000UL) /*!< CCOCLK (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUCALIB_CCOCALIB_Pos         (30UL)         /*!< CCOCALIB (Bit 30)                                     */
 #define R_CTSU2_CTSUCALIB_CCOCALIB_Msk         (0x40000000UL) /*!< CCOCALIB (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_CTSUCALIB_TXREV_Pos            (31UL)         /*!< TXREV (Bit 31)                                        */
 #define R_CTSU2_CTSUCALIB_TXREV_Msk            (0x80000000UL) /*!< TXREV (Bitfield-Mask: 0x01)                           */
/* =======================================================  CTSUDBGR0  ======================================================= */
/* =======================================================  CTSUDBGR1  ======================================================= */
/* ======================================================  CTSUSUCLKA  ======================================================= */
 #define R_CTSU2_CTSUSUCLKA_SUADJ0_Pos          (0UL)          /*!< SUADJ0 (Bit 0)                                        */
 #define R_CTSU2_CTSUSUCLKA_SUADJ0_Msk          (0xffUL)       /*!< SUADJ0 (Bitfield-Mask: 0xff)                          */
 #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Pos        (8UL)          /*!< SUMULTI0 (Bit 8)                                      */
 #define R_CTSU2_CTSUSUCLKA_SUMULTI0_Msk        (0xff00UL)     /*!< SUMULTI0 (Bitfield-Mask: 0xff)                        */
 #define R_CTSU2_CTSUSUCLKA_SUADJ1_Pos          (16UL)         /*!< SUADJ1 (Bit 16)                                       */
 #define R_CTSU2_CTSUSUCLKA_SUADJ1_Msk          (0xff0000UL)   /*!< SUADJ1 (Bitfield-Mask: 0xff)                          */
 #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Pos        (24UL)         /*!< SUMULTI1 (Bit 24)                                     */
 #define R_CTSU2_CTSUSUCLKA_SUMULTI1_Msk        (0xff000000UL) /*!< SUMULTI1 (Bitfield-Mask: 0xff)                        */
/* ======================================================  CTSUSUCLK0  ======================================================= */
/* ======================================================  CTSUSUCLK1  ======================================================= */
/* ======================================================  CTSUSUCLKB  ======================================================= */
 #define R_CTSU2_CTSUSUCLKB_SUADJ2_Pos          (0UL)          /*!< SUADJ2 (Bit 0)                                        */
 #define R_CTSU2_CTSUSUCLKB_SUADJ2_Msk          (0xffUL)       /*!< SUADJ2 (Bitfield-Mask: 0xff)                          */
 #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Pos        (8UL)          /*!< SUMULTI2 (Bit 8)                                      */
 #define R_CTSU2_CTSUSUCLKB_SUMULTI2_Msk        (0xff00UL)     /*!< SUMULTI2 (Bitfield-Mask: 0xff)                        */
 #define R_CTSU2_CTSUSUCLKB_SUADJ3_Pos          (16UL)         /*!< SUADJ3 (Bit 16)                                       */
 #define R_CTSU2_CTSUSUCLKB_SUADJ3_Msk          (0xff0000UL)   /*!< SUADJ3 (Bitfield-Mask: 0xff)                          */
 #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Pos        (24UL)         /*!< SUMULTI3 (Bit 24)                                     */
 #define R_CTSU2_CTSUSUCLKB_SUMULTI3_Msk        (0xff000000UL) /*!< SUMULTI3 (Bitfield-Mask: 0xff)                        */
/* ======================================================  CTSUSUCLK2  ======================================================= */
/* ======================================================  CTSUSUCLK3  ======================================================= */
/* ======================================================  CTSUCFCCNT  ======================================================= */
 #define R_CTSU2_CTSUCFCCNT_CFCCNT_Pos          (0UL)          /*!< CFCCNT (Bit 0)                                        */
 #define R_CTSU2_CTSUCFCCNT_CFCCNT_Msk          (0xffffUL)     /*!< CFCCNT (Bitfield-Mask: 0xffff)                        */
/* ======================================================  CTSUCFCCNTL  ====================================================== */
/* ========================================================  CTSUOPT  ======================================================== */
 #define R_CTSU2_CTSUOPT_CCOCFEN_Pos            (0UL)          /*!< CCOCFEN (Bit 0)                                       */
 #define R_CTSU2_CTSUOPT_CCOCFEN_Msk            (0x1UL)        /*!< CCOCFEN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUOPT_MCACEFN_Pos            (1UL)          /*!< MCACEFN (Bit 1)                                       */
 #define R_CTSU2_CTSUOPT_MCACEFN_Msk            (0x2UL)        /*!< MCACEFN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUOPT_MAJIRIMD_Pos           (2UL)          /*!< MAJIRIMD (Bit 2)                                      */
 #define R_CTSU2_CTSUOPT_MAJIRIMD_Msk           (0x4UL)        /*!< MAJIRIMD (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_CTSUOPT_DTCLESS_Pos            (4UL)          /*!< DTCLESS (Bit 4)                                       */
 #define R_CTSU2_CTSUOPT_DTCLESS_Msk            (0x10UL)       /*!< DTCLESS (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUOPT_MTUCFEN_Pos            (5UL)          /*!< MTUCFEN (Bit 5)                                       */
 #define R_CTSU2_CTSUOPT_MTUCFEN_Msk            (0x20UL)       /*!< MTUCFEN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_CTSUOPT_AJFEN_Pos              (8UL)          /*!< AJFEN (Bit 8)                                         */
 #define R_CTSU2_CTSUOPT_AJFEN_Msk              (0x100UL)      /*!< AJFEN (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUOPT_AJINTC_Pos             (9UL)          /*!< AJINTC (Bit 9)                                        */
 #define R_CTSU2_CTSUOPT_AJINTC_Msk             (0x200UL)      /*!< AJINTC (Bitfield-Mask: 0x01)                          */
 #define R_CTSU2_CTSUOPT_SCACTB_Pos             (16UL)         /*!< SCACTB (Bit 16)                                       */
 #define R_CTSU2_CTSUOPT_SCACTB_Msk             (0xf0000UL)    /*!< SCACTB (Bitfield-Mask: 0x0f)                          */
/* =======================================================  CTSUOPTL  ======================================================== */
/* ==========================================================  AC  =========================================================== */
 #define R_CTSU2_AC_CCOCFEN_Pos                 (0UL)          /*!< CCOCFEN (Bit 0)                                       */
 #define R_CTSU2_AC_CCOCFEN_Msk                 (0x1UL)        /*!< CCOCFEN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_AC_MCACEFN_Pos                 (1UL)          /*!< MCACEFN (Bit 1)                                       */
 #define R_CTSU2_AC_MCACEFN_Msk                 (0x2UL)        /*!< MCACEFN (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_AC_MAJIRIMD_Pos                (2UL)          /*!< MAJIRIMD (Bit 2)                                      */
 #define R_CTSU2_AC_MAJIRIMD_Msk                (0x4UL)        /*!< MAJIRIMD (Bitfield-Mask: 0x01)                        */
 #define R_CTSU2_AC_DTCLESS_Pos                 (4UL)          /*!< DTCLESS (Bit 4)                                       */
 #define R_CTSU2_AC_DTCLESS_Msk                 (0x10UL)       /*!< DTCLESS (Bitfield-Mask: 0x01)                         */
 #define R_CTSU2_AC_MTUCFEN_Pos                 (5UL)          /*!< MTUCFEN (Bit 5)                                       */
 #define R_CTSU2_AC_MTUCFEN_Msk                 (0x20UL)       /*!< MTUCFEN (Bitfield-Mask: 0x01)                         */
/* ==========================================================  AJ  =========================================================== */
 #define R_CTSU2_AJ_AJFEN_Pos                   (0UL)          /*!< AJFEN (Bit 0)                                         */
 #define R_CTSU2_AJ_AJFEN_Msk                   (0x1UL)        /*!< AJFEN (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_AJ_AJINTC_Pos                  (1UL)          /*!< AJINTC (Bit 1)                                        */
 #define R_CTSU2_AJ_AJINTC_Msk                  (0x2UL)        /*!< AJINTC (Bitfield-Mask: 0x01)                          */
/* =======================================================  CTSUOPTH  ======================================================== */
/* =========================================================  ACTB  ========================================================== */
 #define R_CTSU2_ACTB_SCACTB_Pos                (0UL)          /*!< SCACTB (Bit 0)                                        */
 #define R_CTSU2_ACTB_SCACTB_Msk                (0xfUL)        /*!< SCACTB (Bitfield-Mask: 0x0f)                          */
/* ======================================================  CTSUSCNTACT  ====================================================== */
 #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Pos    (0UL)          /*!< SCNTACCOEFF (Bit 0)                                   */
 #define R_CTSU2_CTSUSCNTACT_SCNTACCOEFF_Msk    (0xffffUL)     /*!< SCNTACCOEFF (Bitfield-Mask: 0xffff)                   */
 #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Pos    (16UL)         /*!< SCNTACCOUNT (Bit 16)                                  */
 #define R_CTSU2_CTSUSCNTACT_SCNTACCOUNT_Msk    (0xffff0000UL) /*!< SCNTACCOUNT (Bitfield-Mask: 0xffff)                   */
/* =====================================================  CTSUSCNTACTL  ====================================================== */
/* =====================================================  CTSUSCNTACTH  ====================================================== */
/* =======================================================  CTSUMACT1  ======================================================= */
 #define R_CTSU2_CTSUMACT1_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
 #define R_CTSU2_CTSUMACT1_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
 #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
 #define R_CTSU2_CTSUMACT1_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
/* ======================================================  CTSUMACT1L  ======================================================= */
/* ======================================================  CTSUMACT1H  ======================================================= */
/* =======================================================  CTSUMACT2  ======================================================= */
 #define R_CTSU2_CTSUMACT2_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
 #define R_CTSU2_CTSUMACT2_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
 #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
 #define R_CTSU2_CTSUMACT2_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
/* ======================================================  CTSUMACT2L  ======================================================= */
/* ======================================================  CTSUMACT2H  ======================================================= */
/* =======================================================  CTSUMACT3  ======================================================= */
 #define R_CTSU2_CTSUMACT3_SO_Pos               (0UL)          /*!< SO (Bit 0)                                            */
 #define R_CTSU2_CTSUMACT3_SO_Msk               (0x3ffUL)      /*!< SO (Bitfield-Mask: 0x3ff)                             */
 #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Pos      (16UL)         /*!< OFFSETCOEFF (Bit 16)                                  */
 #define R_CTSU2_CTSUMACT3_OFFSETCOEFF_Msk      (0xffff0000UL) /*!< OFFSETCOEFF (Bitfield-Mask: 0xffff)                   */
/* ======================================================  CTSUMACT3L  ======================================================= */
/* ======================================================  CTSUMACT3H  ======================================================= */
/* =======================================================  CTSUAJCR  ======================================================== */
 #define R_CTSU2_CTSUAJCR_TLOT_Pos              (0UL)          /*!< TLOT (Bit 0)                                          */
 #define R_CTSU2_CTSUAJCR_TLOT_Msk              (0xffUL)       /*!< TLOT (Bitfield-Mask: 0xff)                            */
 #define R_CTSU2_CTSUAJCR_THOT_Pos              (8UL)          /*!< THOT (Bit 8)                                          */
 #define R_CTSU2_CTSUAJCR_THOT_Msk              (0xff00UL)     /*!< THOT (Bitfield-Mask: 0xff)                            */
 #define R_CTSU2_CTSUAJCR_BLINI_Pos             (16UL)         /*!< BLINI (Bit 16)                                        */
 #define R_CTSU2_CTSUAJCR_BLINI_Msk             (0x10000UL)    /*!< BLINI (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_CTSUAJCR_JC_Pos                (20UL)         /*!< JC (Bit 20)                                           */
 #define R_CTSU2_CTSUAJCR_JC_Msk                (0x300000UL)   /*!< JC (Bitfield-Mask: 0x03)                              */
 #define R_CTSU2_CTSUAJCR_AJMMAT_Pos            (24UL)         /*!< AJMMAT (Bit 24)                                       */
 #define R_CTSU2_CTSUAJCR_AJMMAT_Msk            (0xf000000UL)  /*!< AJMMAT (Bitfield-Mask: 0x0f)                          */
 #define R_CTSU2_CTSUAJCR_AJBMAT_Pos            (28UL)         /*!< AJBMAT (Bit 28)                                       */
 #define R_CTSU2_CTSUAJCR_AJBMAT_Msk            (0xf0000000UL) /*!< AJBMAT (Bitfield-Mask: 0x0f)                          */
/* =======================================================  CTSUAJCRL  ======================================================= */
/* =========================================================  AJCR0  ========================================================= */
 #define R_CTSU2_AJCR0_TLOT_Pos                 (0UL)          /*!< TLOT (Bit 0)                                          */
 #define R_CTSU2_AJCR0_TLOT_Msk                 (0xffUL)       /*!< TLOT (Bitfield-Mask: 0xff)                            */
/* =========================================================  AJCR1  ========================================================= */
 #define R_CTSU2_AJCR1_THOT_Pos                 (0UL)          /*!< THOT (Bit 0)                                          */
 #define R_CTSU2_AJCR1_THOT_Msk                 (0xffUL)       /*!< THOT (Bitfield-Mask: 0xff)                            */
/* =======================================================  CTSUAJCRH  ======================================================= */
/* =========================================================  AJCR2  ========================================================= */
 #define R_CTSU2_AJCR2_BLINI_Pos                (0UL)          /*!< BLINI (Bit 0)                                         */
 #define R_CTSU2_AJCR2_BLINI_Msk                (0x1UL)        /*!< BLINI (Bitfield-Mask: 0x01)                           */
 #define R_CTSU2_AJCR2_JC_Pos                   (4UL)          /*!< JC (Bit 4)                                            */
 #define R_CTSU2_AJCR2_JC_Msk                   (0x30UL)       /*!< JC (Bitfield-Mask: 0x03)                              */
/* =========================================================  AJCR3  ========================================================= */
 #define R_CTSU2_AJCR3_AJMMAT_Pos               (0UL)          /*!< AJMMAT (Bit 0)                                        */
 #define R_CTSU2_AJCR3_AJMMAT_Msk               (0xfUL)        /*!< AJMMAT (Bitfield-Mask: 0x0f)                          */
 #define R_CTSU2_AJCR3_AJBMAT_Pos               (4UL)          /*!< AJBMAT (Bit 4)                                        */
 #define R_CTSU2_AJCR3_AJBMAT_Msk               (0xf0UL)       /*!< AJBMAT (Bitfield-Mask: 0x0f)                          */
/* =======================================================  CTSUAJTHR  ======================================================= */
 #define R_CTSU2_CTSUAJTHR_AJTHL_Pos            (0UL)          /*!< AJTHL (Bit 0)                                         */
 #define R_CTSU2_CTSUAJTHR_AJTHL_Msk            (0xffffUL)     /*!< AJTHL (Bitfield-Mask: 0xffff)                         */
 #define R_CTSU2_CTSUAJTHR_AJTHH_Pos            (16UL)         /*!< AJTHH (Bit 16)                                        */
 #define R_CTSU2_CTSUAJTHR_AJTHH_Msk            (0xffff0000UL) /*!< AJTHH (Bitfield-Mask: 0xffff)                         */
/* ======================================================  CTSUAJTHRL  ======================================================= */
/* ======================================================  CTSUAJTHRH  ======================================================= */
/* ======================================================  CTSUAJMMAR  ======================================================= */
 #define R_CTSU2_CTSUAJMMAR_AJMMATI_Pos         (0UL)          /*!< AJMMATI (Bit 0)                                       */
 #define R_CTSU2_CTSUAJMMAR_AJMMATI_Msk         (0xfUL)        /*!< AJMMATI (Bitfield-Mask: 0x0f)                         */
 #define R_CTSU2_CTSUAJMMAR_AJMMR_Pos           (5UL)          /*!< AJMMR (Bit 5)                                         */
 #define R_CTSU2_CTSUAJMMAR_AJMMR_Msk           (0xffffffe0UL) /*!< AJMMR (Bitfield-Mask: 0x7ffffff)                      */
/* ======================================================  CTSUAJMMARL  ====================================================== */
/* ======================================================  CTSUAJMMARH  ====================================================== */
/* ======================================================  CTSUAJBLACT  ====================================================== */
 #define R_CTSU2_CTSUAJBLACT_AJBLACT_Pos        (0UL)          /*!< AJBLACT (Bit 0)                                       */
 #define R_CTSU2_CTSUAJBLACT_AJBLACT_Msk        (0xffffffffUL) /*!< AJBLACT (Bitfield-Mask: 0xffffffff)                   */
/* =====================================================  CTSUAJBLACTL  ====================================================== */
/* =====================================================  CTSUAJBLACTH  ====================================================== */
/* ======================================================  CTSUAJBLAR  ======================================================= */
 #define R_CTSU2_CTSUAJBLAR_AJBLAC_Pos          (0UL)          /*!< AJBLAC (Bit 0)                                        */
 #define R_CTSU2_CTSUAJBLAR_AJBLAC_Msk          (0xffffUL)     /*!< AJBLAC (Bitfield-Mask: 0xffff)                        */
 #define R_CTSU2_CTSUAJBLAR_AJBLAR_Pos          (16UL)         /*!< AJBLAR (Bit 16)                                       */
 #define R_CTSU2_CTSUAJBLAR_AJBLAR_Msk          (0xffff0000UL) /*!< AJBLAR (Bitfield-Mask: 0xffff)                        */
/* ======================================================  CTSUAJBLARL  ====================================================== */
/* ======================================================  CTSUAJBLARH  ====================================================== */
/* =======================================================  CTSUAJRR  ======================================================== */
 #define R_CTSU2_CTSUAJRR_TJR0_Pos              (0UL)          /*!< TJR0 (Bit 0)                                          */
 #define R_CTSU2_CTSUAJRR_TJR0_Msk              (0x1UL)        /*!< TJR0 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUAJRR_TJR1_Pos              (1UL)          /*!< TJR1 (Bit 1)                                          */
 #define R_CTSU2_CTSUAJRR_TJR1_Msk              (0x2UL)        /*!< TJR1 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUAJRR_TJR2_Pos              (2UL)          /*!< TJR2 (Bit 2)                                          */
 #define R_CTSU2_CTSUAJRR_TJR2_Msk              (0x4UL)        /*!< TJR2 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUAJRR_TJR3_Pos              (3UL)          /*!< TJR3 (Bit 3)                                          */
 #define R_CTSU2_CTSUAJRR_TJR3_Msk              (0x8UL)        /*!< TJR3 (Bitfield-Mask: 0x01)                            */
 #define R_CTSU2_CTSUAJRR_FJR_Pos               (4UL)          /*!< FJR (Bit 4)                                           */
 #define R_CTSU2_CTSUAJRR_FJR_Msk               (0x10UL)       /*!< FJR (Bitfield-Mask: 0x01)                             */
 #define R_CTSU2_CTSUAJRR_SJCCR_Pos             (8UL)          /*!< SJCCR (Bit 8)                                         */
 #define R_CTSU2_CTSUAJRR_SJCCR_Msk             (0xff00UL)     /*!< SJCCR (Bitfield-Mask: 0xff)                           */
/* =======================================================  CTSUAJRRL  ======================================================= */
/* =======================================================  CTSUAJRR0  ======================================================= */
/* =======================================================  CTSUAJRR1  ======================================================= */

/* =========================================================================================================================== */
/* ================                                           R_DAC                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  DACR  ========================================================== */
 #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
 #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
 #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
 #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
/* =========================================================  DADR  ========================================================== */
 #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
 #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
/* =========================================================  DADPR  ========================================================= */
 #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
 #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
/* ========================================================  DAADSCR  ======================================================== */
 #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
 #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
/* =======================================================  DAVREFCR  ======================================================== */
 #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
 #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
/* =========================================================  DAPC  ========================================================== */
 #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
 #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
/* ========================================================  DAAMPCR  ======================================================== */
 #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
 #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DAASWCR  ======================================================== */
 #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
 #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
 #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
 #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  DAADUSR  ======================================================== */
 #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
 #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
 #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
 #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */

/* =========================================================================================================================== */
/* ================                                          R_DEBUG                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  DBGSTR  ========================================================= */
 #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
 #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
 #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
 #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
/* =======================================================  DBGSTOPCR  ======================================================= */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
 #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
/* =======================================================  FSBLSTAT  ======================================================== */
 #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
 #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
 #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
 #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
 #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
 #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */

/* =========================================================================================================================== */
/* ================                                           R_DMA                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  DMAST  ========================================================= */
 #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
 #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
/* =========================================================  DMCTL  ========================================================= */
 #define R_DMA_DMCTL_PR_Pos           (0UL)       /*!< PR (Bit 0)                                            */
 #define R_DMA_DMCTL_PR_Msk           (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
 #define R_DMA_DMCTL_ERCH_Pos         (4UL)       /*!< ERCH (Bit 4)                                          */
 #define R_DMA_DMCTL_ERCH_Msk         (0x10UL)    /*!< ERCH (Bitfield-Mask: 0x01)                            */
/* ========================================================  DMECHR  ========================================================= */
 #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
 #define R_DMA_DMECHR_DMECH_Msk       (0xfUL)     /*!< DMECH (Bitfield-Mask: 0x0f)                           */
 #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
 #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
 #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
 #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
/* =========================================================  DELSR  ========================================================= */
 #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
 #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
 #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
 #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */

/* =========================================================================================================================== */
/* ================                                          R_DMAC0                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  DMSAR  ========================================================= */
 #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
 #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DMDAR  ========================================================= */
 #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
 #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DMCRA  ========================================================= */
 #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
 #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
 #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
 #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  DMCRB  ========================================================= */
 #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
 #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
 #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
 #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
/* =========================================================  DMTMD  ========================================================= */
 #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
 #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
 #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
 #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
 #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
 #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
 #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
 #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
 #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
 #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
/* =========================================================  DMINT  ========================================================= */
 #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
 #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
 #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
 #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
 #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
 #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
 #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
 #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
 #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
 #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
/* =========================================================  DMAMD  ========================================================= */
 #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
 #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
 #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
 #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
 #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
 #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
 #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
 #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
 #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
 #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
 #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
 #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
/* =========================================================  DMOFR  ========================================================= */
 #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
 #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  DMCNT  ========================================================= */
 #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
 #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
/* =========================================================  DMREQ  ========================================================= */
 #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
 #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
 #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
 #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
/* =========================================================  DMSTS  ========================================================= */
 #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
 #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
 #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
 #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
 #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
 #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  DMSRR  ========================================================= */
/* =========================================================  DMDRR  ========================================================= */
/* =========================================================  DMSBS  ========================================================= */
 #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
 #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
 #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
 #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
/* =========================================================  DMDBS  ========================================================= */
 #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
 #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
 #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
 #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
/* =========================================================  DMBWR  ========================================================= */
 #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
 #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */

/* =========================================================================================================================== */
/* ================                                           R_DTC                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  DTCCR  ========================================================= */
 #define R_DTC_DTCCR_RRS_Pos            (4UL)          /*!< RRS (Bit 4)                                           */
 #define R_DTC_DTCCR_RRS_Msk            (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
/* ========================================================  DTCVBR  ========================================================= */
 #define R_DTC_DTCVBR_DTCVBR_Pos        (0UL)          /*!< DTCVBR (Bit 0)                                        */
 #define R_DTC_DTCVBR_DTCVBR_Msk        (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DTCADMOD  ======================================================== */
 #define R_DTC_DTCADMOD_SHORT_Pos       (0UL)          /*!< SHORT (Bit 0)                                         */
 #define R_DTC_DTCADMOD_SHORT_Msk       (0x1UL)        /*!< SHORT (Bitfield-Mask: 0x01)                           */
/* =========================================================  DTCST  ========================================================= */
 #define R_DTC_DTCST_DTCST_Pos          (0UL)          /*!< DTCST (Bit 0)                                         */
 #define R_DTC_DTCST_DTCST_Msk          (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
/* ========================================================  DTCSTS  ========================================================= */
 #define R_DTC_DTCSTS_VECN_Pos          (0UL)          /*!< VECN (Bit 0)                                          */
 #define R_DTC_DTCSTS_VECN_Msk          (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
 #define R_DTC_DTCSTS_ACT_Pos           (15UL)         /*!< ACT (Bit 15)                                          */
 #define R_DTC_DTCSTS_ACT_Msk           (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
/* =======================================================  DTCCR_SEC  ======================================================= */
 #define R_DTC_DTCCR_SEC_RRS_Pos        (4UL)          /*!< RRS (Bit 4)                                           */
 #define R_DTC_DTCCR_SEC_RRS_Msk        (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
/* ======================================================  DTCVBR_SEC  ======================================================= */
 #define R_DTC_DTCVBR_SEC_DTCVBR_Pos    (0UL)          /*!< DTCVBR (Bit 0)                                        */
 #define R_DTC_DTCVBR_SEC_DTCVBR_Msk    (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  DTCDISP  ======================================================== */
 #define R_DTC_DTCDISP_DTCDISP_Pos      (0UL)          /*!< DTCDISP (Bit 0)                                       */
 #define R_DTC_DTCDISP_DTCDISP_Msk      (0xffffffffUL) /*!< DTCDISP (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  DTEVR  ========================================================= */
 #define R_DTC_DTEVR_DTEV_Pos           (0UL)          /*!< DTEV (Bit 0)                                          */
 #define R_DTC_DTEVR_DTEV_Msk           (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
 #define R_DTC_DTEVR_DTEVSAM_Pos        (8UL)          /*!< DTEVSAM (Bit 8)                                       */
 #define R_DTC_DTEVR_DTEVSAM_Msk        (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
 #define R_DTC_DTEVR_DTESTA_Pos         (16UL)         /*!< DTESTA (Bit 16)                                       */
 #define R_DTC_DTEVR_DTESTA_Msk         (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
/* ========================================================  DTCIBR  ========================================================= */
 #define R_DTC_DTCIBR_DTCIBR_Pos        (10UL)         /*!< DTCIBR (Bit 10)                                       */
 #define R_DTC_DTCIBR_DTCIBR_Msk        (0xfffffc00UL) /*!< DTCIBR (Bitfield-Mask: 0x3fffff)                      */
/* =========================================================  DTCOR  ========================================================= */
 #define R_DTC_DTCOR_SQTFRL_Pos         (0UL)          /*!< SQTFRL (Bit 0)                                        */
 #define R_DTC_DTCOR_SQTFRL_Msk         (0x1UL)        /*!< SQTFRL (Bitfield-Mask: 0x01)                          */
/* ========================================================  DTCSQE  ========================================================= */
 #define R_DTC_DTCSQE_VECN_Pos          (0UL)          /*!< VECN (Bit 0)                                          */
 #define R_DTC_DTCSQE_VECN_Msk          (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
 #define R_DTC_DTCSQE_ESPSEL_Pos        (15UL)         /*!< ESPSEL (Bit 15)                                       */
 #define R_DTC_DTCSQE_ESPSEL_Msk        (0x8000UL)     /*!< ESPSEL (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                           R_ELC                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  ELCR  ========================================================== */
 #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
 #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
/* ========================================================  ELCSARA  ======================================================== */
 #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
 #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
 #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
 #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
 #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
 #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
/* ========================================================  ELCSARB  ======================================================== */
 #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
 #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
 #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
 #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
 #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
 #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
 #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
 #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
 #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
 #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
 #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
 #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
 #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
 #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
 #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
 #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
 #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
 #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
/* ========================================================  ELCSARC  ======================================================== */
 #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
 #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
 #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
 #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
 #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                       R_FACI_HP_CMD                                       ================ */
/* =========================================================================================================================== */

/* ======================================================  FACI_CMD16  ======================================================= */
/* =======================================================  FACI_CMD8  ======================================================= */

/* =========================================================================================================================== */
/* ================                                         R_FACI_HP                                         ================ */
/* =========================================================================================================================== */

/* ========================================================  FASTAT  ========================================================= */
 #define R_FACI_HP_FASTAT_CFAE_Pos           (7UL)          /*!< CFAE (Bit 7)                                          */
 #define R_FACI_HP_FASTAT_CFAE_Msk           (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
 #define R_FACI_HP_FASTAT_CMDLK_Pos          (4UL)          /*!< CMDLK (Bit 4)                                         */
 #define R_FACI_HP_FASTAT_CMDLK_Msk          (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
 #define R_FACI_HP_FASTAT_DFAE_Pos           (3UL)          /*!< DFAE (Bit 3)                                          */
 #define R_FACI_HP_FASTAT_DFAE_Msk           (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
/* ========================================================  FAEINT  ========================================================= */
 #define R_FACI_HP_FAEINT_CFAEIE_Pos         (7UL)          /*!< CFAEIE (Bit 7)                                        */
 #define R_FACI_HP_FAEINT_CFAEIE_Msk         (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FAEINT_CMDLKIE_Pos        (4UL)          /*!< CMDLKIE (Bit 4)                                       */
 #define R_FACI_HP_FAEINT_CMDLKIE_Msk        (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
 #define R_FACI_HP_FAEINT_DFAEIE_Pos         (3UL)          /*!< DFAEIE (Bit 3)                                        */
 #define R_FACI_HP_FAEINT_DFAEIE_Msk         (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
/* ========================================================  FRDYIE  ========================================================= */
 #define R_FACI_HP_FRDYIE_FRDYIE_Pos         (0UL)          /*!< FRDYIE (Bit 0)                                        */
 #define R_FACI_HP_FRDYIE_FRDYIE_Msk         (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
/* ========================================================  FSADDR  ========================================================= */
 #define R_FACI_HP_FSADDR_FSA_Pos            (0UL)          /*!< FSA (Bit 0)                                           */
 #define R_FACI_HP_FSADDR_FSA_Msk            (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  FEADDR  ========================================================= */
 #define R_FACI_HP_FEADDR_FEA_Pos            (0UL)          /*!< FEA (Bit 0)                                           */
 #define R_FACI_HP_FEADDR_FEA_Msk            (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
/* ========================================================  FMEPROT  ======================================================== */
 #define R_FACI_HP_FMEPROT_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FMEPROT_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FMEPROT_CEPROT_Pos        (0UL)          /*!< CEPROT (Bit 0)                                        */
 #define R_FACI_HP_FMEPROT_CEPROT_Msk        (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
/* ========================================================  FBPROT0  ======================================================== */
 #define R_FACI_HP_FBPROT0_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FBPROT0_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FBPROT0_BPCN0_Pos         (0UL)          /*!< BPCN0 (Bit 0)                                         */
 #define R_FACI_HP_FBPROT0_BPCN0_Msk         (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
/* ========================================================  FBPROT1  ======================================================== */
 #define R_FACI_HP_FBPROT1_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FBPROT1_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FBPROT1_BPCN1_Pos         (0UL)          /*!< BPCN1 (Bit 0)                                         */
 #define R_FACI_HP_FBPROT1_BPCN1_Msk         (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
/* ========================================================  FSTATR  ========================================================= */
 #define R_FACI_HP_FSTATR_ILGCOMERR_Pos      (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
 #define R_FACI_HP_FSTATR_ILGCOMERR_Msk      (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
 #define R_FACI_HP_FSTATR_FESETERR_Pos       (22UL)         /*!< FESETERR (Bit 22)                                     */
 #define R_FACI_HP_FSTATR_FESETERR_Msk       (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
 #define R_FACI_HP_FSTATR_SECERR_Pos         (21UL)         /*!< SECERR (Bit 21)                                       */
 #define R_FACI_HP_FSTATR_SECERR_Msk         (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_OTERR_Pos          (20UL)         /*!< OTERR (Bit 20)                                        */
 #define R_FACI_HP_FSTATR_OTERR_Msk          (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
 #define R_FACI_HP_FSTATR_FRDY_Pos           (15UL)         /*!< FRDY (Bit 15)                                         */
 #define R_FACI_HP_FSTATR_FRDY_Msk           (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
 #define R_FACI_HP_FSTATR_ILGLERR_Pos        (14UL)         /*!< ILGLERR (Bit 14)                                      */
 #define R_FACI_HP_FSTATR_ILGLERR_Msk        (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
 #define R_FACI_HP_FSTATR_ERSERR_Pos         (13UL)         /*!< ERSERR (Bit 13)                                       */
 #define R_FACI_HP_FSTATR_ERSERR_Msk         (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_PRGERR_Pos         (12UL)         /*!< PRGERR (Bit 12)                                       */
 #define R_FACI_HP_FSTATR_PRGERR_Msk         (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_SUSRDY_Pos         (11UL)         /*!< SUSRDY (Bit 11)                                       */
 #define R_FACI_HP_FSTATR_SUSRDY_Msk         (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_DBFULL_Pos         (10UL)         /*!< DBFULL (Bit 10)                                       */
 #define R_FACI_HP_FSTATR_DBFULL_Msk         (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_ERSSPD_Pos         (9UL)          /*!< ERSSPD (Bit 9)                                        */
 #define R_FACI_HP_FSTATR_ERSSPD_Msk         (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_PRGSPD_Pos         (8UL)          /*!< PRGSPD (Bit 8)                                        */
 #define R_FACI_HP_FSTATR_PRGSPD_Msk         (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
 #define R_FACI_HP_FSTATR_FLWEERR_Pos        (6UL)          /*!< FLWEERR (Bit 6)                                       */
 #define R_FACI_HP_FSTATR_FLWEERR_Msk        (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
/* ========================================================  FENTRYR  ======================================================== */
 #define R_FACI_HP_FENTRYR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FENTRYR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FENTRYR_FENTRYD_Pos       (7UL)          /*!< FENTRYD (Bit 7)                                       */
 #define R_FACI_HP_FENTRYR_FENTRYD_Msk       (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
 #define R_FACI_HP_FENTRYR_FENTRYC_Pos       (0UL)          /*!< FENTRYC (Bit 0)                                       */
 #define R_FACI_HP_FENTRYR_FENTRYC_Msk       (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
/* =======================================================  FSUINITR  ======================================================== */
 #define R_FACI_HP_FSUINITR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FSUINITR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FSUINITR_SUINIT_Pos       (0UL)          /*!< SUINIT (Bit 0)                                        */
 #define R_FACI_HP_FSUINITR_SUINIT_Msk       (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
/* =========================================================  FCMDR  ========================================================= */
 #define R_FACI_HP_FCMDR_CMDR_Pos            (8UL)          /*!< CMDR (Bit 8)                                          */
 #define R_FACI_HP_FCMDR_CMDR_Msk            (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
 #define R_FACI_HP_FCMDR_PCMDR_Pos           (0UL)          /*!< PCMDR (Bit 0)                                         */
 #define R_FACI_HP_FCMDR_PCMDR_Msk           (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
/* ========================================================  FBCCNT  ========================================================= */
 #define R_FACI_HP_FBCCNT_BCDIR_Pos          (0UL)          /*!< BCDIR (Bit 0)                                         */
 #define R_FACI_HP_FBCCNT_BCDIR_Msk          (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
/* ========================================================  FBCSTAT  ======================================================== */
 #define R_FACI_HP_FBCSTAT_BCST_Pos          (0UL)          /*!< BCST (Bit 0)                                          */
 #define R_FACI_HP_FBCSTAT_BCST_Msk          (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
/* ========================================================  FPSADDR  ======================================================== */
 #define R_FACI_HP_FPSADDR_PSADR_Pos         (0UL)          /*!< PSADR (Bit 0)                                         */
 #define R_FACI_HP_FPSADDR_PSADR_Msk         (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
/* ========================================================  FBCADDR  ======================================================== */
 #define R_FACI_HP_FBCADDR_BCADR_Pos         (0UL)          /*!< BCADR (Bit 0)                                         */
 #define R_FACI_HP_FBCADDR_BCADR_Msk         (0xffffffUL)   /*!< BCADR (Bitfield-Mask: 0xffffff)                       */
/* ========================================================  FAWMON  ========================================================= */
 #define R_FACI_HP_FAWMON_BTFLG_Pos          (31UL)         /*!< BTFLG (Bit 31)                                        */
 #define R_FACI_HP_FAWMON_BTFLG_Msk          (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
 #define R_FACI_HP_FAWMON_FAWE_Pos           (16UL)         /*!< FAWE (Bit 16)                                         */
 #define R_FACI_HP_FAWMON_FAWE_Msk           (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
 #define R_FACI_HP_FAWMON_FSPR_Pos           (15UL)         /*!< FSPR (Bit 15)                                         */
 #define R_FACI_HP_FAWMON_FSPR_Msk           (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
 #define R_FACI_HP_FAWMON_FAWS_Pos           (0UL)          /*!< FAWS (Bit 0)                                          */
 #define R_FACI_HP_FAWMON_FAWS_Msk           (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
/* =========================================================  FCPSR  ========================================================= */
 #define R_FACI_HP_FCPSR_ESUSPMD_Pos         (0UL)          /*!< ESUSPMD (Bit 0)                                       */
 #define R_FACI_HP_FCPSR_ESUSPMD_Msk         (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
/* ========================================================  FPCKAR  ========================================================= */
 #define R_FACI_HP_FPCKAR_KEY_Pos            (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FPCKAR_KEY_Msk            (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FPCKAR_PCKA_Pos           (0UL)          /*!< PCKA (Bit 0)                                          */
 #define R_FACI_HP_FPCKAR_PCKA_Msk           (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
/* ========================================================  FSUACR  ========================================================= */
 #define R_FACI_HP_FSUACR_KEY_Pos            (8UL)          /*!< KEY (Bit 8)                                           */
 #define R_FACI_HP_FSUACR_KEY_Msk            (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_FACI_HP_FSUACR_SAS_Pos            (0UL)          /*!< SAS (Bit 0)                                           */
 #define R_FACI_HP_FSUACR_SAS_Msk            (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
/* =======================================================  FCNTSELR  ======================================================== */
 #define R_FACI_HP_FCNTSELR_CNTSEL_Pos       (0UL)          /*!< CNTSEL (Bit 0)                                        */
 #define R_FACI_HP_FCNTSELR_CNTSEL_Msk       (0x7UL)        /*!< CNTSEL (Bitfield-Mask: 0x07)                          */
/* ======================================================  FCNTDATAR0  ======================================================= */
 #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Pos    (0UL)          /*!< CNTRDAT (Bit 0)                                       */
 #define R_FACI_HP_FCNTDATAR0_CNTRDAT_Msk    (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FCNTDATAR1  ======================================================= */
 #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Pos    (0UL)          /*!< CNTRDAT (Bit 0)                                       */
 #define R_FACI_HP_FCNTDATAR1_CNTRDAT_Msk    (0xffffffffUL) /*!< CNTRDAT (Bitfield-Mask: 0xffffffff)                   */

/* =========================================================================================================================== */
/* ================                                         R_FACI_LP                                         ================ */
/* =========================================================================================================================== */

/* ========================================================  DFLCTL  ========================================================= */
/* =========================================================  FPMCR  ========================================================= */
 #define R_FACI_LP_FPMCR_FMS2_Pos           (7UL)      /*!< FMS2 (Bit 7)                                          */
 #define R_FACI_LP_FPMCR_FMS2_Msk           (0x80UL)   /*!< FMS2 (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FPMCR_VLPE_Pos           (6UL)      /*!< VLPE (Bit 6)                                          */
 #define R_FACI_LP_FPMCR_VLPE_Msk           (0x40UL)   /*!< VLPE (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FPMCR_FMS1_Pos           (4UL)      /*!< FMS1 (Bit 4)                                          */
 #define R_FACI_LP_FPMCR_FMS1_Msk           (0x10UL)   /*!< FMS1 (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FPMCR_RPDIS_Pos          (3UL)      /*!< RPDIS (Bit 3)                                         */
 #define R_FACI_LP_FPMCR_RPDIS_Msk          (0x8UL)    /*!< RPDIS (Bitfield-Mask: 0x01)                           */
 #define R_FACI_LP_FPMCR_FMS0_Pos           (1UL)      /*!< FMS0 (Bit 1)                                          */
 #define R_FACI_LP_FPMCR_FMS0_Msk           (0x2UL)    /*!< FMS0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  FASR  ========================================================== */
 #define R_FACI_LP_FASR_EXS_Pos             (0UL)      /*!< EXS (Bit 0)                                           */
 #define R_FACI_LP_FASR_EXS_Msk             (0x1UL)    /*!< EXS (Bitfield-Mask: 0x01)                             */
/* =========================================================  FSARL  ========================================================= */
 #define R_FACI_LP_FSARL_FSAR15_0_Pos       (0UL)      /*!< FSAR15_0 (Bit 0)                                      */
 #define R_FACI_LP_FSARL_FSAR15_0_Msk       (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff)                      */
/* =========================================================  FSARH  ========================================================= */
 #define R_FACI_LP_FSARH_FSAR31_25_Pos      (9UL)      /*!< FSAR31_25 (Bit 9)                                     */
 #define R_FACI_LP_FSARH_FSAR31_25_Msk      (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f)                       */
 #define R_FACI_LP_FSARH_FSAR20_16_Pos      (0UL)      /*!< FSAR20_16 (Bit 0)                                     */
 #define R_FACI_LP_FSARH_FSAR20_16_Msk      (0x1fUL)   /*!< FSAR20_16 (Bitfield-Mask: 0x1f)                       */
/* ==========================================================  FCR  ========================================================== */
 #define R_FACI_LP_FCR_OPST_Pos             (7UL)      /*!< OPST (Bit 7)                                          */
 #define R_FACI_LP_FCR_OPST_Msk             (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FCR_STOP_Pos             (6UL)      /*!< STOP (Bit 6)                                          */
 #define R_FACI_LP_FCR_STOP_Msk             (0x40UL)   /*!< STOP (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FCR_DRC_Pos              (4UL)      /*!< DRC (Bit 4)                                           */
 #define R_FACI_LP_FCR_DRC_Msk              (0x10UL)   /*!< DRC (Bitfield-Mask: 0x01)                             */
 #define R_FACI_LP_FCR_CMD_Pos              (0UL)      /*!< CMD (Bit 0)                                           */
 #define R_FACI_LP_FCR_CMD_Msk              (0xfUL)    /*!< CMD (Bitfield-Mask: 0x0f)                             */
/* =========================================================  FEARL  ========================================================= */
 #define R_FACI_LP_FEARL_FEAR15_0_Pos       (0UL)      /*!< FEAR15_0 (Bit 0)                                      */
 #define R_FACI_LP_FEARL_FEAR15_0_Msk       (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff)                      */
/* =========================================================  FEARH  ========================================================= */
 #define R_FACI_LP_FEARH_FEAR31_25_Pos      (9UL)      /*!< FEAR31_25 (Bit 9)                                     */
 #define R_FACI_LP_FEARH_FEAR31_25_Msk      (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f)                       */
 #define R_FACI_LP_FEARH_FEAR20_16_Pos      (0UL)      /*!< FEAR20_16 (Bit 0)                                     */
 #define R_FACI_LP_FEARH_FEAR20_16_Msk      (0x1fUL)   /*!< FEAR20_16 (Bitfield-Mask: 0x1f)                       */
/* ========================================================  FRESETR  ======================================================== */
 #define R_FACI_LP_FRESETR_FRESET_Pos       (0UL)      /*!< FRESET (Bit 0)                                        */
 #define R_FACI_LP_FRESETR_FRESET_Msk       (0x1UL)    /*!< FRESET (Bitfield-Mask: 0x01)                          */
/* =======================================================  FSTATR00  ======================================================== */
 #define R_FACI_LP_FSTATR00_EILGLERR_Pos    (5UL)      /*!< EILGLERR (Bit 5)                                      */
 #define R_FACI_LP_FSTATR00_EILGLERR_Msk    (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
 #define R_FACI_LP_FSTATR00_ILGLERR_Pos     (4UL)      /*!< ILGLERR (Bit 4)                                       */
 #define R_FACI_LP_FSTATR00_ILGLERR_Msk     (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
 #define R_FACI_LP_FSTATR00_BCERR0_Pos      (3UL)      /*!< BCERR0 (Bit 3)                                        */
 #define R_FACI_LP_FSTATR00_BCERR0_Msk      (0x8UL)    /*!< BCERR0 (Bitfield-Mask: 0x01)                          */
 #define R_FACI_LP_FSTATR00_PRGERR01_Pos    (2UL)      /*!< PRGERR01 (Bit 2)                                      */
 #define R_FACI_LP_FSTATR00_PRGERR01_Msk    (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
 #define R_FACI_LP_FSTATR00_PRGERR0_Pos     (1UL)      /*!< PRGERR0 (Bit 1)                                       */
 #define R_FACI_LP_FSTATR00_PRGERR0_Msk     (0x2UL)    /*!< PRGERR0 (Bitfield-Mask: 0x01)                         */
 #define R_FACI_LP_FSTATR00_ERERR0_Pos      (0UL)      /*!< ERERR0 (Bit 0)                                        */
 #define R_FACI_LP_FSTATR00_ERERR0_Msk      (0x1UL)    /*!< ERERR0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  FSTATR1  ======================================================== */
 #define R_FACI_LP_FSTATR1_EXRDY_Pos        (7UL)      /*!< EXRDY (Bit 7)                                         */
 #define R_FACI_LP_FSTATR1_EXRDY_Msk        (0x80UL)   /*!< EXRDY (Bitfield-Mask: 0x01)                           */
 #define R_FACI_LP_FSTATR1_FRDY_Pos         (6UL)      /*!< FRDY (Bit 6)                                          */
 #define R_FACI_LP_FSTATR1_FRDY_Msk         (0x40UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FSTATR1_DRRDY_Pos        (1UL)      /*!< DRRDY (Bit 1)                                         */
 #define R_FACI_LP_FSTATR1_DRRDY_Msk        (0x2UL)    /*!< DRRDY (Bitfield-Mask: 0x01)                           */
/* =========================================================  FWBL0  ========================================================= */
 #define R_FACI_LP_FWBL0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
 #define R_FACI_LP_FWBL0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  FWBH0  ========================================================= */
 #define R_FACI_LP_FWBH0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
 #define R_FACI_LP_FWBH0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
/* =======================================================  FSTATR01  ======================================================== */
 #define R_FACI_LP_FSTATR01_BCERR1_Pos      (3UL)      /*!< BCERR1 (Bit 3)                                        */
 #define R_FACI_LP_FSTATR01_BCERR1_Msk      (0x8UL)    /*!< BCERR1 (Bitfield-Mask: 0x01)                          */
 #define R_FACI_LP_FSTATR01_PRGERR1_Pos     (1UL)      /*!< PRGERR1 (Bit 1)                                       */
 #define R_FACI_LP_FSTATR01_PRGERR1_Msk     (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
 #define R_FACI_LP_FSTATR01_ERERR1_Pos      (0UL)      /*!< ERERR1 (Bit 0)                                        */
 #define R_FACI_LP_FSTATR01_ERERR1_Msk      (0x1UL)    /*!< ERERR1 (Bitfield-Mask: 0x01)                          */
/* =========================================================  FWBL1  ========================================================= */
 #define R_FACI_LP_FWBL1_WDATA47_32_Pos     (0UL)      /*!< WDATA47_32 (Bit 0)                                    */
 #define R_FACI_LP_FWBL1_WDATA47_32_Msk     (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff)                    */
/* =========================================================  FWBH1  ========================================================= */
 #define R_FACI_LP_FWBH1_WDATA63_48_Pos     (0UL)      /*!< WDATA63_48 (Bit 0)                                    */
 #define R_FACI_LP_FWBH1_WDATA63_48_Msk     (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff)                    */
/* =========================================================  FRBL1  ========================================================= */
 #define R_FACI_LP_FRBL1_RDATA47_32_Pos     (0UL)      /*!< RDATA47_32 (Bit 0)                                    */
 #define R_FACI_LP_FRBL1_RDATA47_32_Msk     (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff)                    */
/* =========================================================  FRBH1  ========================================================= */
 #define R_FACI_LP_FRBH1_RDATA63_48_Pos     (0UL)      /*!< RDATA63_48 (Bit 0)                                    */
 #define R_FACI_LP_FRBH1_RDATA63_48_Msk     (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff)                    */
/* ==========================================================  FPR  ========================================================== */
 #define R_FACI_LP_FPR_FPR_Pos              (0UL)      /*!< FPR (Bit 0)                                           */
 #define R_FACI_LP_FPR_FPR_Msk              (0xffUL)   /*!< FPR (Bitfield-Mask: 0xff)                             */
/* =========================================================  FPSR  ========================================================== */
 #define R_FACI_LP_FPSR_PERR_Pos            (0UL)      /*!< PERR (Bit 0)                                          */
 #define R_FACI_LP_FPSR_PERR_Msk            (0x1UL)    /*!< PERR (Bitfield-Mask: 0x01)                            */
/* =========================================================  FRBL0  ========================================================= */
 #define R_FACI_LP_FRBL0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
 #define R_FACI_LP_FRBL0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  FRBH0  ========================================================= */
 #define R_FACI_LP_FRBH0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
 #define R_FACI_LP_FRBH0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
/* =========================================================  FSCMR  ========================================================= */
 #define R_FACI_LP_FSCMR_FSPR_Pos           (14UL)     /*!< FSPR (Bit 14)                                         */
 #define R_FACI_LP_FSCMR_FSPR_Msk           (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FSCMR_SASMF_Pos          (8UL)      /*!< SASMF (Bit 8)                                         */
 #define R_FACI_LP_FSCMR_SASMF_Msk          (0x100UL)  /*!< SASMF (Bitfield-Mask: 0x01)                           */
/* ========================================================  FAWSMR  ========================================================= */
 #define R_FACI_LP_FAWSMR_FAWS_Pos          (0UL)      /*!< FAWS (Bit 0)                                          */
 #define R_FACI_LP_FAWSMR_FAWS_Msk          (0xfffUL)  /*!< FAWS (Bitfield-Mask: 0xfff)                           */
/* ========================================================  FAWEMR  ========================================================= */
 #define R_FACI_LP_FAWEMR_FAWE_Pos          (0UL)      /*!< FAWE (Bit 0)                                          */
 #define R_FACI_LP_FAWEMR_FAWE_Msk          (0xfffUL)  /*!< FAWE (Bitfield-Mask: 0xfff)                           */
/* =========================================================  FISR  ========================================================== */
 #define R_FACI_LP_FISR_SAS_Pos             (6UL)      /*!< SAS (Bit 6)                                           */
 #define R_FACI_LP_FISR_SAS_Msk             (0xc0UL)   /*!< SAS (Bitfield-Mask: 0x03)                             */
 #define R_FACI_LP_FISR_PCKA_Pos            (0UL)      /*!< PCKA (Bit 0)                                          */
 #define R_FACI_LP_FISR_PCKA_Msk            (0x3fUL)   /*!< PCKA (Bitfield-Mask: 0x3f)                            */
/* =========================================================  FEXCR  ========================================================= */
 #define R_FACI_LP_FEXCR_OPST_Pos           (7UL)      /*!< OPST (Bit 7)                                          */
 #define R_FACI_LP_FEXCR_OPST_Msk           (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
 #define R_FACI_LP_FEXCR_CMD_Pos            (0UL)      /*!< CMD (Bit 0)                                           */
 #define R_FACI_LP_FEXCR_CMD_Msk            (0x7UL)    /*!< CMD (Bitfield-Mask: 0x07)                             */
/* =========================================================  FEAML  ========================================================= */
 #define R_FACI_LP_FEAML_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
 #define R_FACI_LP_FEAML_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
/* =========================================================  FEAMH  ========================================================= */
 #define R_FACI_LP_FEAMH_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
 #define R_FACI_LP_FEAMH_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
/* ========================================================  FSTATR2  ======================================================== */
 #define R_FACI_LP_FSTATR2_EILGLERR_Pos     (5UL)      /*!< EILGLERR (Bit 5)                                      */
 #define R_FACI_LP_FSTATR2_EILGLERR_Msk     (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
 #define R_FACI_LP_FSTATR2_ILGLERR_Pos      (4UL)      /*!< ILGLERR (Bit 4)                                       */
 #define R_FACI_LP_FSTATR2_ILGLERR_Msk      (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
 #define R_FACI_LP_FSTATR2_BCERR_Pos        (3UL)      /*!< BCERR (Bit 3)                                         */
 #define R_FACI_LP_FSTATR2_BCERR_Msk        (0x8UL)    /*!< BCERR (Bitfield-Mask: 0x01)                           */
 #define R_FACI_LP_FSTATR2_PRGERR01_Pos     (2UL)      /*!< PRGERR01 (Bit 2)                                      */
 #define R_FACI_LP_FSTATR2_PRGERR01_Msk     (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
 #define R_FACI_LP_FSTATR2_PRGERR1_Pos      (1UL)      /*!< PRGERR1 (Bit 1)                                       */
 #define R_FACI_LP_FSTATR2_PRGERR1_Msk      (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
 #define R_FACI_LP_FSTATR2_ERERR_Pos        (0UL)      /*!< ERERR (Bit 0)                                         */
 #define R_FACI_LP_FSTATR2_ERERR_Msk        (0x1UL)    /*!< ERERR (Bitfield-Mask: 0x01)                           */
/* ========================================================  FCTLFR  ========================================================= */
 #define R_FACI_LP_FCTLFR_BANKSWP_Pos       (0UL)      /*!< BANKSWP (Bit 0)                                       */
 #define R_FACI_LP_FCTLFR_BANKSWP_Msk       (0x7UL)    /*!< BANKSWP (Bitfield-Mask: 0x07)                         */
/* ======================================================  FENTRYR_MF4  ====================================================== */
/* ========================================================  FENTRYR  ======================================================== */
/* ========================================================  FLWAITR  ======================================================== */
/* =======================================================  FLDWAITR  ======================================================== */
 #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos    (0UL)      /*!< FLDWAIT1 (Bit 0)                                      */
 #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk    (0x1UL)    /*!< FLDWAIT1 (Bitfield-Mask: 0x01)                        */
/* =========================================================  PFBER  ========================================================= */
/* ========================================================  FBKPGCR  ======================================================== */
 #define R_FACI_LP_FBKPGCR_BKPGEN_Pos       (0UL)      /*!< BKPGEN (Bit 0)                                        */
 #define R_FACI_LP_FBKPGCR_BKPGEN_Msk       (0x1UL)    /*!< BKPGEN (Bitfield-Mask: 0x01)                          */
 #define R_FACI_LP_FBKPGCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
 #define R_FACI_LP_FBKPGCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
/* ========================================================  FBKSWCR  ======================================================== */
 #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos     (0UL)      /*!< BKSWUPEN (Bit 0)                                      */
 #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk     (0x1UL)    /*!< BKSWUPEN (Bitfield-Mask: 0x01)                        */
 #define R_FACI_LP_FBKSWCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
 #define R_FACI_LP_FBKSWCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
/* ========================================================  HIOTRM  ========================================================= */
 #define R_FACI_LP_HIOTRM_HIOTRM_Pos        (0UL)      /*!< HIOTRM (Bit 0)                                        */
 #define R_FACI_LP_HIOTRM_HIOTRM_Msk        (0x3fUL)   /*!< HIOTRM (Bitfield-Mask: 0x3f)                          */
/* ========================================================  FLMODE  ========================================================= */
 #define R_FACI_LP_FLMODE_MODE_Pos          (6UL)      /*!< MODE (Bit 6)                                          */
 #define R_FACI_LP_FLMODE_MODE_Msk          (0xc0UL)   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* ========================================================  FLMWRP  ========================================================= */
 #define R_FACI_LP_FLMWRP_FLMWEN_Pos        (0UL)      /*!< FLMWEN (Bit 0)                                        */
 #define R_FACI_LP_FLMWRP_FLMWEN_Msk        (0x1UL)    /*!< FLMWEN (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                        R_CTSUTRIM                                         ================ */
/* =========================================================================================================================== */

/* =======================================================  CTSUTRIMA  ======================================================= */
 #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Pos    (24UL)         /*!< SUADJTRIM (Bit 24)                                    */
 #define R_CTSUTRIM_CTSUTRIMA_SUADJTRIM_Msk    (0xff000000UL) /*!< SUADJTRIM (Bitfield-Mask: 0xff)                       */
 #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Pos       (16UL)         /*!< SUADJD (Bit 16)                                       */
 #define R_CTSUTRIM_CTSUTRIMA_SUADJD_Msk       (0xff0000UL)   /*!< SUADJD (Bitfield-Mask: 0xff)                          */
 #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Pos      (8UL)          /*!< DACTRIM (Bit 8)                                       */
 #define R_CTSUTRIM_CTSUTRIMA_DACTRIM_Msk      (0xff00UL)     /*!< DACTRIM (Bitfield-Mask: 0xff)                         */
 #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Pos        (0UL)          /*!< RTRIM (Bit 0)                                         */
 #define R_CTSUTRIM_CTSUTRIMA_RTRIM_Msk        (0xffUL)       /*!< RTRIM (Bitfield-Mask: 0xff)                           */
/* =======================================================  CTSUTRIMB  ======================================================= */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Pos     (24UL)         /*!< TRESULT3 (Bit 24)                                     */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT3_Msk     (0xff000000UL) /*!< TRESULT3 (Bitfield-Mask: 0xff)                        */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Pos     (16UL)         /*!< TRESULT2 (Bit 16)                                     */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT2_Msk     (0xff0000UL)   /*!< TRESULT2 (Bitfield-Mask: 0xff)                        */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Pos     (8UL)          /*!< TRESULT1 (Bit 8)                                      */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT1_Msk     (0xff00UL)     /*!< TRESULT1 (Bitfield-Mask: 0xff)                        */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Pos     (0UL)          /*!< TRESULT0 (Bit 0)                                      */
 #define R_CTSUTRIM_CTSUTRIMB_TRESULT0_Msk     (0xffUL)       /*!< TRESULT0 (Bitfield-Mask: 0xff)                        */

/* =========================================================================================================================== */
/* ================                                         R_FCACHE                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  FCACHEE  ======================================================== */
 #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)      /*!< FCACHEEN (Bit 0)                                      */
 #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)    /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
/* =======================================================  FCACHEIV  ======================================================== */
 #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)      /*!< FCACHEIV (Bit 0)                                      */
 #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)    /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
/* =========================================================  FLWT  ========================================================== */
 #define R_FCACHE_FLWT_FLWT_Pos            (0UL)      /*!< FLWT (Bit 0)                                          */
 #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)    /*!< FLWT (Bitfield-Mask: 0x07)                            */
/* =========================================================  FSAR  ========================================================== */
 #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)      /*!< FLWTSA (Bit 0)                                        */
 #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)    /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
 #define R_FCACHE_FSAR_PFBERSA_Pos         (1UL)      /*!< PFBERSA (Bit 1)                                       */
 #define R_FCACHE_FSAR_PFBERSA_Msk         (0x2UL)    /*!< PFBERSA (Bitfield-Mask: 0x01)                         */
 #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)      /*!< FCKMHZSA (Bit 8)                                      */
 #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL)  /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
 #define R_FCACHE_FSAR_FACICOMISA_Pos      (9UL)      /*!< FACICOMISA (Bit 9)                                    */
 #define R_FCACHE_FSAR_FACICOMISA_Msk      (0x200UL)  /*!< FACICOMISA (Bitfield-Mask: 0x01)                      */
 #define R_FCACHE_FSAR_FACICOMRSA_Pos      (10UL)     /*!< FACICOMRSA (Bit 10)                                   */
 #define R_FCACHE_FSAR_FACICOMRSA_Msk      (0x400UL)  /*!< FACICOMRSA (Bitfield-Mask: 0x01)                      */
 #define R_FCACHE_FSAR_DFLCTLSA_Pos        (15UL)     /*!< DFLCTLSA (Bit 15)                                     */
 #define R_FCACHE_FSAR_DFLCTLSA_Msk        (0x8000UL) /*!< DFLCTLSA (Bitfield-Mask: 0x01)                        */

/* =========================================================================================================================== */
/* ================                                          R_GPT0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  GTWP  ========================================================== */
 #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
 #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
 #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
 #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
 #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
 #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
 #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
 #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
 #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
/* =========================================================  GTSTR  ========================================================= */
 #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
 #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
/* =========================================================  GTSTP  ========================================================= */
 #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
 #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
/* =========================================================  GTCLR  ========================================================= */
 #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
 #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
/* =========================================================  GTSSR  ========================================================= */
 #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
 #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
 #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
 #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
 #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
 #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
 #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
 #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
 #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
 #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
 #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
 #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
 #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
/* =========================================================  GTPSR  ========================================================= */
 #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
 #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
 #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
 #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
 #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
 #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
 #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
 #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
 #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
 #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
 #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
 #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
 #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
/* =========================================================  GTCSR  ========================================================= */
 #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
 #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
 #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
 #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
 #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
 #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
 #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
 #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
 #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
 #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
 #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
 #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
 #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
 #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
 #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
 #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTUPSR  ========================================================= */
 #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
 #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
 #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
 #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
 #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
 #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
 #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
 #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
 #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
 #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
 #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
 #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
 #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
 #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTDNSR  ========================================================= */
 #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
 #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
 #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
 #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
 #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
 #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
 #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
 #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
 #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
 #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
 #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
 #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
 #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
 #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTICASR  ======================================================== */
 #define R_GPT0_GTICASR_ASOC_Pos           (24UL)         /*!< ASOC (Bit 24)                                         */
 #define R_GPT0_GTICASR_ASOC_Msk           (0x1000000UL)  /*!< ASOC (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
 #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
 #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
 #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
 #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
 #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
 #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
 #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
 #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
 #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
 #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
 #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTICBSR  ======================================================== */
 #define R_GPT0_GTICBSR_BSOC_Pos           (24UL)         /*!< BSOC (Bit 24)                                         */
 #define R_GPT0_GTICBSR_BSOC_Msk           (0x1000000UL)  /*!< BSOC (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
 #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
 #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
 #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
 #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
 #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
 #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
 #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
 #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
 #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
 #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
 #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
/* =========================================================  GTCR  ========================================================== */
 #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
 #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
 #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
 #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
 #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
 #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
 #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
 #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
 #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
 #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
 #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTCR_BINV_Pos              (5UL)          /*!< BINV (Bit 5)                                          */
 #define R_GPT0_GTCR_BINV_Msk              (0x20UL)       /*!< BINV (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTCR_AINV_Pos              (4UL)          /*!< AINV (Bit 4)                                          */
 #define R_GPT0_GTCR_AINV_Msk              (0x10UL)       /*!< AINV (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
 #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
/* =======================================================  GTUDDTYC  ======================================================== */
 #define R_GPT0_GTUDDTYC_OABDTYT_Pos       (28UL)         /*!< OABDTYT (Bit 28)                                      */
 #define R_GPT0_GTUDDTYC_OABDTYT_Msk       (0x10000000UL) /*!< OABDTYT (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
 #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
 #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
 #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
 #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
 #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
 #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
 #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
 #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
/* =========================================================  GTIOR  ========================================================= */
 #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
 #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
 #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
 #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
 #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
 #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
 #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
 #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
 #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
 #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
 #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
 #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
 #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
 #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
 #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
 #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
 #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
 #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
 #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
 #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
/* ========================================================  GTINTAD  ======================================================== */
 #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
 #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
 #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
 #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
 #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
 #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
 #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
 #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
 #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
 #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
 #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
 #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTINTAD_GTINTPR_Pos        (6UL)          /*!< GTINTPR (Bit 6)                                       */
 #define R_GPT0_GTINTAD_GTINTPR_Msk        (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
 #define R_GPT0_GTINTAD_GTINT_Pos          (0UL)          /*!< GTINT (Bit 0)                                         */
 #define R_GPT0_GTINTAD_GTINT_Msk          (0x1UL)        /*!< GTINT (Bitfield-Mask: 0x01)                           */
/* =========================================================  GTST  ========================================================== */
 #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
 #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
 #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
 #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
 #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
 #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
 #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
 #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
 #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
 #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
 #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
 #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
 #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
 #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
 #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
 #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
 #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
 #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
 #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
 #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
/* =========================================================  GTBER  ========================================================= */
 #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
 #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
 #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
 #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
 #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
 #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
 #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
 #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
 #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
 #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
 #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
 #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
 #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
 #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
 #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
 #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
/* =========================================================  GTITC  ========================================================= */
 #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
 #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
 #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
 #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
 #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
 #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
 #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
 #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
 #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
 #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
 #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
 #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
 #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
/* =========================================================  GTCNT  ========================================================= */
 #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
 #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTCCR  ========================================================= */
 #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
 #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTPR  ========================================================== */
 #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
 #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  GTPBR  ========================================================= */
 #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
 #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  GTPDBR  ========================================================= */
 #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
 #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  GTADTRA  ======================================================== */
 #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
 #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  GTADTRB  ======================================================== */
 #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
 #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  GTADTBRA  ======================================================== */
 #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
 #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  GTADTBRB  ======================================================== */
 #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
 #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  GTADTDBRA  ======================================================= */
 #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
 #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  GTADTDBRB  ======================================================= */
 #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
 #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  GTDTCR  ========================================================= */
 #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
 #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
 #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
 #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
 #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
/* =========================================================  GTDVU  ========================================================= */
 #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
 #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTDVD  ========================================================= */
 #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
 #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTDBU  ========================================================= */
 #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
 #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTDBD  ========================================================= */
 #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
 #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  GTSOS  ========================================================= */
 #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
 #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
/* ========================================================  GTSOTR  ========================================================= */
 #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
 #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
/* ========================================================  GTADSMR  ======================================================== */
 #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
 #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
 #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
 #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
 #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTEITC  ========================================================= */
 #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
 #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
 #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
 #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
 #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
 #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
 #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
 #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
 #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
 #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
 #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
 #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
/* =======================================================  GTEITLI1  ======================================================== */
 #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
 #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
 #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
 #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
 #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
 #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
 #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
 #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
 #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
/* =======================================================  GTEITLI2  ======================================================== */
 #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
 #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
 #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
 #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
/* ========================================================  GTEITLB  ======================================================== */
 #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
 #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
 #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
 #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
 #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
 #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
 #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
 #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
 #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
 #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
 #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
/* ========================================================  GTICLF  ========================================================= */
 #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
 #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
 #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
 #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
 #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
 #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
 #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
/* =========================================================  GTPC  ========================================================== */
 #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
 #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
 #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
 #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
/* =======================================================  GTADCMSC  ======================================================== */
 #define R_GPT0_GTADCMSC_ADCMSCNT_Pos      (12UL)         /*!< ADCMSCNT (Bit 12)                                     */
 #define R_GPT0_GTADCMSC_ADCMSCNT_Msk      (0xf000UL)     /*!< ADCMSCNT (Bitfield-Mask: 0x0f)                        */
 #define R_GPT0_GTADCMSC_ADCMSCNTIV_Pos    (8UL)          /*!< ADCMSCNTIV (Bit 8)                                    */
 #define R_GPT0_GTADCMSC_ADCMSCNTIV_Msk    (0xf00UL)      /*!< ADCMSCNTIV (Bitfield-Mask: 0x0f)                      */
 #define R_GPT0_GTADCMSC_ADCMST_Pos        (4UL)          /*!< ADCMST (Bit 4)                                        */
 #define R_GPT0_GTADCMSC_ADCMST_Msk        (0xf0UL)       /*!< ADCMST (Bitfield-Mask: 0x0f)                          */
 #define R_GPT0_GTADCMSC_ADCMSC_Pos        (0UL)          /*!< ADCMSC (Bit 0)                                        */
 #define R_GPT0_GTADCMSC_ADCMSC_Msk        (0x3UL)        /*!< ADCMSC (Bitfield-Mask: 0x03)                          */
/* =======================================================  GTADCMSS  ======================================================== */
 #define R_GPT0_GTADCMSS_ADCMSAL_Pos       (0UL)          /*!< ADCMSAL (Bit 0)                                       */
 #define R_GPT0_GTADCMSS_ADCMSAL_Msk       (0x7UL)        /*!< ADCMSAL (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTADCMSS_ADCMSBL_Pos       (4UL)          /*!< ADCMSBL (Bit 4)                                       */
 #define R_GPT0_GTADCMSS_ADCMSBL_Msk       (0x70UL)       /*!< ADCMSBL (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTADCMSS_ADCMBSA_Pos       (16UL)         /*!< ADCMBSA (Bit 16)                                      */
 #define R_GPT0_GTADCMSS_ADCMBSA_Msk       (0x70000UL)    /*!< ADCMBSA (Bitfield-Mask: 0x07)                         */
 #define R_GPT0_GTADCMSS_ADCMBSB_Pos       (20UL)         /*!< ADCMBSB (Bit 20)                                      */
 #define R_GPT0_GTADCMSS_ADCMBSB_Msk       (0x700000UL)   /*!< ADCMBSB (Bitfield-Mask: 0x07)                         */
/* ========================================================  GTSECSR  ======================================================== */
 #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
 #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
 #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
 #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
 #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
 #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
 #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
 #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
 #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
 #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
 #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
 #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
/* ========================================================  GTSECR  ========================================================= */
 #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
 #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
 #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
 #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
 #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
 #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
 #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
 #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
 #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
 #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
 #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
 #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
 #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
 #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
/* ========================================================  GTBER2  ========================================================= */
 #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
 #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
 #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
 #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
 #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
 #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
 #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
 #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
 #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
 #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
 #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
 #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
 #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
 #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
 #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
 #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
 #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
 #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
 #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
 #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
 #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
 #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
/* ========================================================  GTOLBR  ========================================================= */
 #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
 #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
 #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
 #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
/* ========================================================  GTICCR  ========================================================= */
 #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
 #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
 #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
 #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
 #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
 #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
 #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
 #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
 #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
 #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
 #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
 #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
 #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
 #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
 #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
 #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
 #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
 #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
 #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
 #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
 #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
 #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
 #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
 #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */

/* =========================================================================================================================== */
/* ================                                         R_GPT_OPS                                         ================ */
/* =========================================================================================================================== */

/* =========================================================  OPSCR  ========================================================= */
 #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
 #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
 #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
 #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
 #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
 #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
 #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
 #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
 #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
 #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
 #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
 #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
 #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
 #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
 #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
 #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
 #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
 #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
 #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
 #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
 #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
 #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
 #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
 #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
 #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
 #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
 #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
 #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
 #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
 #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
 #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
 #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
 #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
 #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */

/* =========================================================================================================================== */
/* ================                                        R_GPT_POEG0                                        ================ */
/* =========================================================================================================================== */

/* =========================================================  POEGG  ========================================================= */
 #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
 #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
 #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
 #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
 #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
 #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
 #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
 #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
 #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
 #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
 #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
 #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
 #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
 #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
 #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
 #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
 #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
 #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
 #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
 #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
 #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
 #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
 #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
 #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
/* ========================================================  GTONCWP  ======================================================== */
 #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
 #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
 #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
 #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
/* ========================================================  GTONCCR  ======================================================== */
 #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
 #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
 #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
 #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
 #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
 #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */

/* =========================================================================================================================== */
/* ================                                           R_ICU                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  IRQCR  ========================================================= */
 #define R_ICU_IRQCR_FLTEN_Pos              (7UL)          /*!< FLTEN (Bit 7)                                         */
 #define R_ICU_IRQCR_FLTEN_Msk              (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_IRQCR_FCLKSEL_Pos            (4UL)          /*!< FCLKSEL (Bit 4)                                       */
 #define R_ICU_IRQCR_FCLKSEL_Msk            (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
 #define R_ICU_IRQCR_LOCOSEL_Pos            (3UL)          /*!< LOCOSEL (Bit 3)                                       */
 #define R_ICU_IRQCR_LOCOSEL_Msk            (0x8UL)        /*!< LOCOSEL (Bitfield-Mask: 0x01)                         */
 #define R_ICU_IRQCR_IRQMD_Pos              (0UL)          /*!< IRQMD (Bit 0)                                         */
 #define R_ICU_IRQCR_IRQMD_Msk              (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
/* =========================================================  NMISR  ========================================================= */
 #define R_ICU_NMISR_SPEST_Pos              (12UL)         /*!< SPEST (Bit 12)                                        */
 #define R_ICU_NMISR_SPEST_Msk              (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_BUSMST_Pos             (11UL)         /*!< BUSMST (Bit 11)                                       */
 #define R_ICU_NMISR_BUSMST_Msk             (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_BUSSST_Pos             (10UL)         /*!< BUSSST (Bit 10)                                       */
 #define R_ICU_NMISR_BUSSST_Msk             (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_RECCST_Pos             (9UL)          /*!< RECCST (Bit 9)                                        */
 #define R_ICU_NMISR_RECCST_Msk             (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_RPEST_Pos              (8UL)          /*!< RPEST (Bit 8)                                         */
 #define R_ICU_NMISR_RPEST_Msk              (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_NMIST_Pos              (7UL)          /*!< NMIST (Bit 7)                                         */
 #define R_ICU_NMISR_NMIST_Msk              (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_OSTST_Pos              (6UL)          /*!< OSTST (Bit 6)                                         */
 #define R_ICU_NMISR_OSTST_Msk              (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_VBATTST_Pos            (4UL)          /*!< VBATTST (Bit 4)                                       */
 #define R_ICU_NMISR_VBATTST_Msk            (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMISR_LVD2ST_Pos             (3UL)          /*!< LVD2ST (Bit 3)                                        */
 #define R_ICU_NMISR_LVD2ST_Msk             (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_LVD1ST_Pos             (2UL)          /*!< LVD1ST (Bit 2)                                        */
 #define R_ICU_NMISR_LVD1ST_Msk             (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_WDTST_Pos              (1UL)          /*!< WDTST (Bit 1)                                         */
 #define R_ICU_NMISR_WDTST_Msk              (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_IWDTST_Pos             (0UL)          /*!< IWDTST (Bit 0)                                        */
 #define R_ICU_NMISR_IWDTST_Msk             (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMISR_TZFST_Pos              (13UL)         /*!< TZFST (Bit 13)                                        */
 #define R_ICU_NMISR_TZFST_Msk              (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMISR_CPEST_Pos              (15UL)         /*!< CPEST (Bit 15)                                        */
 #define R_ICU_NMISR_CPEST_Msk              (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
/* =========================================================  NMIER  ========================================================= */
 #define R_ICU_NMIER_SPEEN_Pos              (12UL)         /*!< SPEEN (Bit 12)                                        */
 #define R_ICU_NMIER_SPEEN_Msk              (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_BUSMEN_Pos             (11UL)         /*!< BUSMEN (Bit 11)                                       */
 #define R_ICU_NMIER_BUSMEN_Msk             (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_BUSSEN_Pos             (10UL)         /*!< BUSSEN (Bit 10)                                       */
 #define R_ICU_NMIER_BUSSEN_Msk             (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_RECCEN_Pos             (9UL)          /*!< RECCEN (Bit 9)                                        */
 #define R_ICU_NMIER_RECCEN_Msk             (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_RPEEN_Pos              (8UL)          /*!< RPEEN (Bit 8)                                         */
 #define R_ICU_NMIER_RPEEN_Msk              (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_NMIEN_Pos              (7UL)          /*!< NMIEN (Bit 7)                                         */
 #define R_ICU_NMIER_NMIEN_Msk              (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_OSTEN_Pos              (6UL)          /*!< OSTEN (Bit 6)                                         */
 #define R_ICU_NMIER_OSTEN_Msk              (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_VBATTEN_Pos            (4UL)          /*!< VBATTEN (Bit 4)                                       */
 #define R_ICU_NMIER_VBATTEN_Msk            (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMIER_LVD2EN_Pos             (3UL)          /*!< LVD2EN (Bit 3)                                        */
 #define R_ICU_NMIER_LVD2EN_Msk             (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_LVD1EN_Pos             (2UL)          /*!< LVD1EN (Bit 2)                                        */
 #define R_ICU_NMIER_LVD1EN_Msk             (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_WDTEN_Pos              (1UL)          /*!< WDTEN (Bit 1)                                         */
 #define R_ICU_NMIER_WDTEN_Msk              (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_IWDTEN_Pos             (0UL)          /*!< IWDTEN (Bit 0)                                        */
 #define R_ICU_NMIER_IWDTEN_Msk             (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMIER_TZFEN_Pos              (13UL)         /*!< TZFEN (Bit 13)                                        */
 #define R_ICU_NMIER_TZFEN_Msk              (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_NMIER_CPEEN_Pos              (15UL)         /*!< CPEEN (Bit 15)                                        */
 #define R_ICU_NMIER_CPEEN_Msk              (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  NMICLR  ========================================================= */
 #define R_ICU_NMICLR_SPECLR_Pos            (12UL)         /*!< SPECLR (Bit 12)                                       */
 #define R_ICU_NMICLR_SPECLR_Msk            (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_BUSMCLR_Pos           (11UL)         /*!< BUSMCLR (Bit 11)                                      */
 #define R_ICU_NMICLR_BUSMCLR_Msk           (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_BUSSCLR_Pos           (10UL)         /*!< BUSSCLR (Bit 10)                                      */
 #define R_ICU_NMICLR_BUSSCLR_Msk           (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_RECCCLR_Pos           (9UL)          /*!< RECCCLR (Bit 9)                                       */
 #define R_ICU_NMICLR_RECCCLR_Msk           (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_RPECLR_Pos            (8UL)          /*!< RPECLR (Bit 8)                                        */
 #define R_ICU_NMICLR_RPECLR_Msk            (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_NMICLR_Pos            (7UL)          /*!< NMICLR (Bit 7)                                        */
 #define R_ICU_NMICLR_NMICLR_Msk            (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_OSTCLR_Pos            (6UL)          /*!< OSTCLR (Bit 6)                                        */
 #define R_ICU_NMICLR_OSTCLR_Msk            (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_VBATTCLR_Pos          (4UL)          /*!< VBATTCLR (Bit 4)                                      */
 #define R_ICU_NMICLR_VBATTCLR_Msk          (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
 #define R_ICU_NMICLR_LVD2CLR_Pos           (3UL)          /*!< LVD2CLR (Bit 3)                                       */
 #define R_ICU_NMICLR_LVD2CLR_Msk           (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_LVD1CLR_Pos           (2UL)          /*!< LVD1CLR (Bit 2)                                       */
 #define R_ICU_NMICLR_LVD1CLR_Msk           (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_WDTCLR_Pos            (1UL)          /*!< WDTCLR (Bit 1)                                        */
 #define R_ICU_NMICLR_WDTCLR_Msk            (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_IWDTCLR_Pos           (0UL)          /*!< IWDTCLR (Bit 0)                                       */
 #define R_ICU_NMICLR_IWDTCLR_Msk           (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
 #define R_ICU_NMICLR_TZFCLR_Pos            (13UL)         /*!< TZFCLR (Bit 13)                                       */
 #define R_ICU_NMICLR_TZFCLR_Msk            (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICLR_CPECLR_Pos            (15UL)         /*!< CPECLR (Bit 15)                                       */
 #define R_ICU_NMICLR_CPECLR_Msk            (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
/* =========================================================  NMICR  ========================================================= */
 #define R_ICU_NMICR_NFLTEN_Pos             (7UL)          /*!< NFLTEN (Bit 7)                                        */
 #define R_ICU_NMICR_NFLTEN_Msk             (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
 #define R_ICU_NMICR_NFCLKSEL_Pos           (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
 #define R_ICU_NMICR_NFCLKSEL_Msk           (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
 #define R_ICU_NMICR_NMIMD_Pos              (0UL)          /*!< NMIMD (Bit 0)                                         */
 #define R_ICU_NMICR_NMIMD_Msk              (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
/* =========================================================  IELSR  ========================================================= */
 #define R_ICU_IELSR_DTCE_Pos               (24UL)         /*!< DTCE (Bit 24)                                         */
 #define R_ICU_IELSR_DTCE_Msk               (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
 #define R_ICU_IELSR_IR_Pos                 (16UL)         /*!< IR (Bit 16)                                           */
 #define R_ICU_IELSR_IR_Msk                 (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
 #define R_ICU_IELSR_IELS_Pos               (0UL)          /*!< IELS (Bit 0)                                          */
 #define R_ICU_IELSR_IELS_Msk               (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  DELSR  ========================================================= */
 #define R_ICU_DELSR_IR_Pos                 (16UL)         /*!< IR (Bit 16)                                           */
 #define R_ICU_DELSR_IR_Msk                 (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
 #define R_ICU_DELSR_DELS_Pos               (0UL)          /*!< DELS (Bit 0)                                          */
 #define R_ICU_DELSR_DELS_Msk               (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
/* ========================================================  SELSR0  ========================================================= */
 #define R_ICU_SELSR0_SELS_Pos              (0UL)          /*!< SELS (Bit 0)                                          */
 #define R_ICU_SELSR0_SELS_Msk              (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  WUPEN  ========================================================= */
 #define R_ICU_WUPEN_IIC0WUPEN_Pos          (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
 #define R_ICU_WUPEN_IIC0WUPEN_Msk          (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
 #define R_ICU_WUPEN_AGT1CBWUPEN_Pos        (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
 #define R_ICU_WUPEN_AGT1CBWUPEN_Msk        (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN_AGT1CAWUPEN_Pos        (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
 #define R_ICU_WUPEN_AGT1CAWUPEN_Msk        (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN_AGT1UDWUPEN_Pos        (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
 #define R_ICU_WUPEN_AGT1UDWUPEN_Msk        (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN_USBFSWUPEN_Pos         (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
 #define R_ICU_WUPEN_USBFSWUPEN_Msk         (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
 #define R_ICU_WUPEN_USBHSWUPEN_Pos         (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
 #define R_ICU_WUPEN_USBHSWUPEN_Msk         (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
 #define R_ICU_WUPEN_RTCPRDWUPEN_Pos        (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
 #define R_ICU_WUPEN_RTCPRDWUPEN_Msk        (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN_RTCALMWUPEN_Pos        (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
 #define R_ICU_WUPEN_RTCALMWUPEN_Msk        (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos       (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
 #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk       (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
 #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos       (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
 #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk       (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
 #define R_ICU_WUPEN_VBATTWUPEN_Pos         (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
 #define R_ICU_WUPEN_VBATTWUPEN_Msk         (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
 #define R_ICU_WUPEN_LVD2WUPEN_Pos          (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
 #define R_ICU_WUPEN_LVD2WUPEN_Msk          (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
 #define R_ICU_WUPEN_LVD1WUPEN_Pos          (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
 #define R_ICU_WUPEN_LVD1WUPEN_Msk          (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
 #define R_ICU_WUPEN_KEYWUPEN_Pos           (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
 #define R_ICU_WUPEN_KEYWUPEN_Msk           (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
 #define R_ICU_WUPEN_IWDTWUPEN_Pos          (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
 #define R_ICU_WUPEN_IWDTWUPEN_Msk          (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
 #define R_ICU_WUPEN_IRQWUPEN_Pos           (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
 #define R_ICU_WUPEN_IRQWUPEN_Msk           (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  WUPEN1  ========================================================= */
 #define R_ICU_WUPEN1_SOSCWUPEN_Pos         (7UL)          /*!< SOSCWUPEN (Bit 7)                                     */
 #define R_ICU_WUPEN1_SOSCWUPEN_Msk         (0x80UL)       /*!< SOSCWUPEN (Bitfield-Mask: 0x01)                       */
 #define R_ICU_WUPEN1_I3CWUPEN_Pos          (11UL)         /*!< I3CWUPEN (Bit 11)                                     */
 #define R_ICU_WUPEN1_I3CWUPEN_Msk          (0x800UL)      /*!< I3CWUPEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  WUPEN2  ========================================================= */
 #define R_ICU_WUPEN2_INTUR0WUPEN_Pos       (0UL)          /*!< INTUR0WUPEN (Bit 0)                                   */
 #define R_ICU_WUPEN2_INTUR0WUPEN_Msk       (0x1UL)        /*!< INTUR0WUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN2_INTURE0WUPEN_Pos      (1UL)          /*!< INTURE0WUPEN (Bit 1)                                  */
 #define R_ICU_WUPEN2_INTURE0WUPEN_Msk      (0x2UL)        /*!< INTURE0WUPEN (Bitfield-Mask: 0x01)                    */
 #define R_ICU_WUPEN2_INTUR1WUPEN_Pos       (2UL)          /*!< INTUR1WUPEN (Bit 2)                                   */
 #define R_ICU_WUPEN2_INTUR1WUPEN_Msk       (0x4UL)        /*!< INTUR1WUPEN (Bitfield-Mask: 0x01)                     */
 #define R_ICU_WUPEN2_INTURE1WUPEN_Pos      (3UL)          /*!< INTURE1WUPEN (Bit 3)                                  */
 #define R_ICU_WUPEN2_INTURE1WUPEN_Msk      (0x8UL)        /*!< INTURE1WUPEN (Bitfield-Mask: 0x01)                    */
 #define R_ICU_WUPEN2_EXLVDVBATWUPEN_Pos    (4UL)          /*!< EXLVDVBATWUPEN (Bit 4)                                */
 #define R_ICU_WUPEN2_EXLVDVBATWUPEN_Msk    (0x10UL)       /*!< EXLVDVBATWUPEN (Bitfield-Mask: 0x01)                  */
 #define R_ICU_WUPEN2_LVDVRTCWUPEN_Pos      (5UL)          /*!< LVDVRTCWUPEN (Bit 5)                                  */
 #define R_ICU_WUPEN2_LVDVRTCWUPEN_Msk      (0x20UL)       /*!< LVDVRTCWUPEN (Bitfield-Mask: 0x01)                    */
 #define R_ICU_WUPEN2_EXLVDWUPEN_Pos        (6UL)          /*!< EXLVDWUPEN (Bit 6)                                    */
 #define R_ICU_WUPEN2_EXLVDWUPEN_Msk        (0x40UL)       /*!< EXLVDWUPEN (Bitfield-Mask: 0x01)                      */
/* =========================================================  IELEN  ========================================================= */
 #define R_ICU_IELEN_IELEN_Pos              (1UL)          /*!< IELEN (Bit 1)                                         */
 #define R_ICU_IELEN_IELEN_Msk              (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
 #define R_ICU_IELEN_RTCINTEN_Pos           (0UL)          /*!< RTCINTEN (Bit 0)                                      */
 #define R_ICU_IELEN_RTCINTEN_Msk           (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */

/* =========================================================================================================================== */
/* ================                                          R_IIC0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  ICCR1  ========================================================= */
 #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
 #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
 #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
 #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
 #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
 #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
 #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
 #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
 #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
 #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
/* =========================================================  ICCR2  ========================================================= */
 #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
 #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
 #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
 #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
 #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
 #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
 #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
 #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
 #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
/* =========================================================  ICMR1  ========================================================= */
 #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
 #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
 #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
 #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
 #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
 #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
/* =========================================================  ICMR2  ========================================================= */
 #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
 #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
 #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
 #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
 #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
 #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
 #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
/* =========================================================  ICMR3  ========================================================= */
 #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
 #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
 #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
 #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
 #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
 #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
 #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
 #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
/* =========================================================  ICFER  ========================================================= */
 #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
 #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
 #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
 #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
 #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
 #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
 #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
 #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
 #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
/* =========================================================  ICSER  ========================================================= */
 #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
 #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
 #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
 #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
 #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
 #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
 #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
/* =========================================================  ICIER  ========================================================= */
 #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
 #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
 #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
 #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
 #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
 #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
 #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
 #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
 #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
/* =========================================================  ICSR1  ========================================================= */
 #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
 #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
 #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
 #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
 #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
 #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
 #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  ICSR2  ========================================================= */
 #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
 #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
 #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
 #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
 #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
 #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
 #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
 #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
 #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
 #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
/* =========================================================  ICBRL  ========================================================= */
 #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
 #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
/* =========================================================  ICBRH  ========================================================= */
 #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
 #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
/* =========================================================  ICDRT  ========================================================= */
 #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
 #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
/* =========================================================  ICDRR  ========================================================= */
 #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
 #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
/* =========================================================  ICWUR  ========================================================= */
 #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
 #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
 #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
 #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
 #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
 #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
 #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
 #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
/* ========================================================  ICWUR2  ========================================================= */
 #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
 #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
 #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
 #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
 #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
 #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                          R_IRDA                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  IRCR  ========================================================== */
 #define R_IRDA_IRCR_IRE_Pos        (7UL)    /*!< IRE (Bit 7)                                           */
 #define R_IRDA_IRCR_IRE_Msk        (0x80UL) /*!< IRE (Bitfield-Mask: 0x01)                             */
 #define R_IRDA_IRCR_IRTXINV_Pos    (3UL)    /*!< IRTXINV (Bit 3)                                       */
 #define R_IRDA_IRCR_IRTXINV_Msk    (0x8UL)  /*!< IRTXINV (Bitfield-Mask: 0x01)                         */
 #define R_IRDA_IRCR_IRRXINV_Pos    (2UL)    /*!< IRRXINV (Bit 2)                                       */
 #define R_IRDA_IRCR_IRRXINV_Msk    (0x4UL)  /*!< IRRXINV (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                          R_IWDT                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  IWDTRR  ========================================================= */
 #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
 #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
/* ========================================================  IWDTCR  ========================================================= */
 #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
 #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
 #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
 #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
 #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
 #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
 #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
 #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
/* ========================================================  IWDTSR  ========================================================= */
 #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
 #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
 #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
 #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
 #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
 #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
/* ========================================================  IWDTRCR  ======================================================== */
 #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
 #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
/* =======================================================  IWDTCSTPR  ======================================================= */
 #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
 #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                          R_I3C0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  PRTS  ========================================================== */
 #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
 #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
/* =========================================================  CECTL  ========================================================= */
 #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
 #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
/* =========================================================  BCTL  ========================================================== */
 #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
 #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
 #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
 #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
 #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
 #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
 #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
/* ========================================================  MSDVAD  ========================================================= */
 #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
 #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
 #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
 #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
/* ========================================================  RSTCTL  ========================================================= */
 #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
 #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
 #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
 #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
 #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
 #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
 #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
 #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_RSTCTL_HCMDQRST_Pos     (9UL)          /*!< HCMDQRST (Bit 9)                                      */
 #define R_I3C0_RSTCTL_HCMDQRST_Msk     (0x200UL)      /*!< HCMDQRST (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_RSTCTL_HRSPQRST_Pos     (10UL)         /*!< HRSPQRST (Bit 10)                                     */
 #define R_I3C0_RSTCTL_HRSPQRST_Msk     (0x400UL)      /*!< HRSPQRST (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_RSTCTL_HTDBRST_Pos      (11UL)         /*!< HTDBRST (Bit 11)                                      */
 #define R_I3C0_RSTCTL_HTDBRST_Msk      (0x800UL)      /*!< HTDBRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_HRDBRST_Pos      (12UL)         /*!< HRDBRST (Bit 12)                                      */
 #define R_I3C0_RSTCTL_HRDBRST_Msk      (0x1000UL)     /*!< HRDBRST (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
 #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
/* =========================================================  PRSST  ========================================================= */
 #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
 #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
 #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
 #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
/* =========================================================  INST  ========================================================== */
 #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
 #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
/* =========================================================  INSTE  ========================================================= */
 #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
 #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
/* =========================================================  INIE  ========================================================== */
 #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
 #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INSTFC  ========================================================= */
 #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
 #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
/* =========================================================  DVCT  ========================================================== */
 #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
 #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
/* ========================================================  IBINCTL  ======================================================== */
 #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
 #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
 #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
 #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
/* =========================================================  BFCTL  ========================================================= */
 #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
 #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
 #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
 #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
 #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
 #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
 #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
 #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
/* =========================================================  SVCTL  ========================================================= */
 #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
 #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
 #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
 #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
 #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
 #define R_I3C0_SVCTL_SVAEn_Msk         (0x70000UL)    /*!< SVAEn (Bitfield-Mask: 0x07)                           */
/* =======================================================  REFCKCTL  ======================================================== */
 #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
 #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
/* =========================================================  STDBR  ========================================================= */
 #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
 #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
 #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
 #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
 #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
 #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
 #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
 #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
 #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
 #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
/* =========================================================  EXTBR  ========================================================= */
 #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
 #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
 #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
 #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
 #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
 #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
 #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
 #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
/* ========================================================  BFRECDT  ======================================================== */
 #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
 #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
/* ========================================================  BAVLCDT  ======================================================== */
 #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
 #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
/* ========================================================  BIDLCDT  ======================================================== */
 #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
 #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
/* ========================================================  OUTCTL  ========================================================= */
 #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
 #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
 #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
 #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
 #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
 #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
 #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
 #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
/* =========================================================  INCTL  ========================================================= */
 #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
 #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
 #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
 #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
/* ========================================================  TMOCTL  ========================================================= */
 #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
 #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
 #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
 #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
 #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
 #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
/* =========================================================  WUCTL  ========================================================= */
 #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
 #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
 #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
 #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
 #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
/* ========================================================  ACKCTL  ========================================================= */
 #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
 #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
 #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
 #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
/* =======================================================  SCSTRCTL  ======================================================== */
 #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
 #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
 #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
/* =======================================================  SCSTLCTL  ======================================================== */
 #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
 #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
 #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
 #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
 #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
 #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
 #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
/* ========================================================  SVTDLG0  ======================================================== */
 #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
 #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
/* =========================================================  STCTL  ========================================================= */
 #define R_I3C0_STCTL_STOE_Pos          (0UL)          /*!< STOE (Bit 0)                                          */
 #define R_I3C0_STCTL_STOE_Msk          (0x1UL)        /*!< STOE (Bitfield-Mask: 0x01)                            */
/* =========================================================  ATCTL  ========================================================= */
 #define R_I3C0_ATCTL_ATTRGS_Pos        (0UL)          /*!< ATTRGS (Bit 0)                                        */
 #define R_I3C0_ATCTL_ATTRGS_Msk        (0x1UL)        /*!< ATTRGS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_ATCTL_MREFOE_Pos        (1UL)          /*!< MREFOE (Bit 1)                                        */
 #define R_I3C0_ATCTL_MREFOE_Msk        (0x2UL)        /*!< MREFOE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_ATCTL_AMEOE_Pos         (2UL)          /*!< AMEOE (Bit 2)                                         */
 #define R_I3C0_ATCTL_AMEOE_Msk         (0x4UL)        /*!< AMEOE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_ATCTL_CDIV_Pos          (8UL)          /*!< CDIV (Bit 8)                                          */
 #define R_I3C0_ATCTL_CDIV_Msk          (0xff00UL)     /*!< CDIV (Bitfield-Mask: 0xff)                            */
/* =========================================================  ATTRG  ========================================================= */
 #define R_I3C0_ATTRG_ATSTRG_Pos        (0UL)          /*!< ATSTRG (Bit 0)                                        */
 #define R_I3C0_ATTRG_ATSTRG_Msk        (0x1UL)        /*!< ATSTRG (Bitfield-Mask: 0x01)                          */
/* ========================================================  ATCCNTE  ======================================================== */
 #define R_I3C0_ATCCNTE_ATCE_Pos        (0UL)          /*!< ATCE (Bit 0)                                          */
 #define R_I3C0_ATCCNTE_ATCE_Msk        (0x1UL)        /*!< ATCE (Bitfield-Mask: 0x01)                            */
/* ========================================================  CNDCTL  ========================================================= */
 #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
 #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
 #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
 #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
/* ========================================================  NCMDQP  ========================================================= */
/* ========================================================  NRSPQP  ========================================================= */
/* ========================================================  NTDTBP0  ======================================================== */
/* ========================================================  NIBIQP  ========================================================= */
/* =========================================================  NRSQP  ========================================================= */
/* ========================================================  HCMDQP  ========================================================= */
 #define R_I3C0_HCMDQP_HCMDQP_Pos       (0UL)          /*!< HCMDQP (Bit 0)                                        */
 #define R_I3C0_HCMDQP_HCMDQP_Msk       (0xffffffffUL) /*!< HCMDQP (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HRSPQP  ========================================================= */
 #define R_I3C0_HRSPQP_HRSPQP_Pos       (0UL)          /*!< HRSPQP (Bit 0)                                        */
 #define R_I3C0_HRSPQP_HRSPQP_Msk       (0xffffffffUL) /*!< HRSPQP (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HTDTBP  ========================================================= */
 #define R_I3C0_HTDTBP_HTDTBP_Pos       (0UL)          /*!< HTDTBP (Bit 0)                                        */
 #define R_I3C0_HTDTBP_HTDTBP_Msk       (0xffffffffUL) /*!< HTDTBP (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  NQTHCTL  ======================================================== */
 #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
 #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
 #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
 #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
 #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
 #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
/* =======================================================  NTBTHCTL0  ======================================================= */
 #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
 #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
 #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
 #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
 #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
/* =======================================================  NRQTHCTL  ======================================================== */
 #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
 #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
/* ========================================================  HQTHCTL  ======================================================== */
 #define R_I3C0_HQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
 #define R_I3C0_HQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_HQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
 #define R_I3C0_HQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
/* =======================================================  HTBTHCTL  ======================================================== */
 #define R_I3C0_HTBTHCTL_TXDBTH_Pos     (0UL)          /*!< TXDBTH (Bit 0)                                        */
 #define R_I3C0_HTBTHCTL_TXDBTH_Msk     (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_HTBTHCTL_RXDBTH_Pos     (8UL)          /*!< RXDBTH (Bit 8)                                        */
 #define R_I3C0_HTBTHCTL_RXDBTH_Msk     (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_HTBTHCTL_TXSTTH_Pos     (16UL)         /*!< TXSTTH (Bit 16)                                       */
 #define R_I3C0_HTBTHCTL_TXSTTH_Msk     (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
 #define R_I3C0_HTBTHCTL_RXSTTH_Pos     (24UL)         /*!< RXSTTH (Bit 24)                                       */
 #define R_I3C0_HTBTHCTL_RXSTTH_Msk     (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
/* ==========================================================  BST  ========================================================== */
 #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
 #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
 #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
 #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
 #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
 #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
 #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
 #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BST_WUCNDDF_Pos         (24UL)         /*!< WUCNDDF (Bit 24)                                      */
 #define R_I3C0_BST_WUCNDDF_Msk         (0x1000000UL)  /*!< WUCNDDF (Bitfield-Mask: 0x01)                         */
/* =========================================================  BSTE  ========================================================== */
 #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
 #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
 #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
 #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
 #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
 #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
 #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
 #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BSTE_WUCNDDE_Pos        (24UL)         /*!< WUCNDDE (Bit 24)                                      */
 #define R_I3C0_BSTE_WUCNDDE_Msk        (0x1000000UL)  /*!< WUCNDDE (Bitfield-Mask: 0x01)                         */
/* ==========================================================  BIE  ========================================================== */
 #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
 #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
 #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
 #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
 #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
 #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
 #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
 #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BIE_WUCNDDIE_Pos        (24UL)         /*!< WUCNDDIE (Bit 24)                                     */
 #define R_I3C0_BIE_WUCNDDIE_Msk        (0x1000000UL)  /*!< WUCNDDIE (Bitfield-Mask: 0x01)                        */
/* =========================================================  BSTFC  ========================================================= */
 #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
 #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
 #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
 #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
 #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
 #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
 #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
 #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BSTFC_WUCNDDFC_Pos      (24UL)         /*!< WUCNDDFC (Bit 24)                                     */
 #define R_I3C0_BSTFC_WUCNDDFC_Msk      (0x1000000UL)  /*!< WUCNDDFC (Bitfield-Mask: 0x01)                        */
/* =========================================================  NTST  ========================================================== */
 #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
 #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
 #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
 #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
 #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
 #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
 #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
 #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
 #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
/* =========================================================  NTSTE  ========================================================= */
 #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
 #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
 #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
 #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
 #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
 #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
 #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
 #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
 #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
 #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
/* =========================================================  NTIE  ========================================================== */
 #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
 #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
 #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
 #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
 #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
 #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
 #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
 #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
 #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
/* ========================================================  NTSTFC  ========================================================= */
 #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
 #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
 #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
 #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
 #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
 #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
 #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
 #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
 #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
/* =========================================================  HTST  ========================================================== */
 #define R_I3C0_HTST_TDBEF_Pos          (0UL)          /*!< TDBEF (Bit 0)                                         */
 #define R_I3C0_HTST_TDBEF_Msk          (0x1UL)        /*!< TDBEF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTST_RDBFF_Pos          (1UL)          /*!< RDBFF (Bit 1)                                         */
 #define R_I3C0_HTST_RDBFF_Msk          (0x2UL)        /*!< RDBFF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
 #define R_I3C0_HTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
 #define R_I3C0_HTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
 #define R_I3C0_HTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
 #define R_I3C0_HTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
/* =========================================================  HTSTE  ========================================================= */
 #define R_I3C0_HTSTE_TDBEE_Pos         (0UL)          /*!< TDBEE (Bit 0)                                         */
 #define R_I3C0_HTSTE_TDBEE_Msk         (0x1UL)        /*!< TDBEE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTSTE_RDBFE_Pos         (1UL)          /*!< RDBFE (Bit 1)                                         */
 #define R_I3C0_HTSTE_RDBFE_Msk         (0x2UL)        /*!< RDBFE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
 #define R_I3C0_HTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
 #define R_I3C0_HTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
 #define R_I3C0_HTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_HTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
 #define R_I3C0_HTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
/* =========================================================  HTIE  ========================================================== */
 #define R_I3C0_HTIE_TDBEIE_Pos         (0UL)          /*!< TDBEIE (Bit 0)                                        */
 #define R_I3C0_HTIE_TDBEIE_Msk         (0x1UL)        /*!< TDBEIE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTIE_RDBFIE_Pos         (1UL)          /*!< RDBFIE (Bit 1)                                        */
 #define R_I3C0_HTIE_RDBFIE_Msk         (0x2UL)        /*!< RDBFIE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
 #define R_I3C0_HTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_HTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
 #define R_I3C0_HTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_HTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
 #define R_I3C0_HTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
 #define R_I3C0_HTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
/* ========================================================  HTSTFC  ========================================================= */
 #define R_I3C0_HTSTFC_TDBEFC_Pos       (0UL)          /*!< TDBEFC (Bit 0)                                        */
 #define R_I3C0_HTSTFC_TDBEFC_Msk       (0x1UL)        /*!< TDBEFC (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTSTFC_RDBFFC_Pos       (1UL)          /*!< RDBFFC (Bit 1)                                        */
 #define R_I3C0_HTSTFC_RDBFFC_Msk       (0x2UL)        /*!< RDBFFC (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
 #define R_I3C0_HTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_HTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
 #define R_I3C0_HTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_HTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
 #define R_I3C0_HTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_HTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
 #define R_I3C0_HTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
/* =========================================================  BCST  ========================================================== */
 #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
 #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
 #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
 #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
/* =========================================================  SVST  ========================================================== */
 #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
 #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
 #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
 #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
 #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
 #define R_I3C0_SVST_SVAFn_Msk          (0x70000UL)    /*!< SVAFn (Bitfield-Mask: 0x07)                           */
/* =========================================================  WUST  ========================================================== */
 #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
 #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
/* ========================================================  MRCCPT  ========================================================= */
 #define R_I3C0_MRCCPT_MRCCPT_Pos       (0UL)          /*!< MRCCPT (Bit 0)                                        */
 #define R_I3C0_MRCCPT_MRCCPT_Msk       (0xffffffffUL) /*!< MRCCPT (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  DATBAS0  ======================================================== */
 #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS1  ======================================================== */
 #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS2  ======================================================== */
 #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS3  ======================================================== */
 #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS4  ======================================================== */
 #define R_I3C0_DATBAS4_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS4_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS4_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS4_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS4_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS4_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS4_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS4_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS4_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS4_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS4_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS4_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS4_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS4_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS4_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS4_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS5  ======================================================== */
 #define R_I3C0_DATBAS5_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS5_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS5_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS5_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS5_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS5_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS5_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS5_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS5_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS5_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS5_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS5_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS5_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS5_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS5_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS5_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS6  ======================================================== */
 #define R_I3C0_DATBAS6_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS6_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS6_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS6_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS6_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS6_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS6_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS6_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS6_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS6_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS6_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS6_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS6_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS6_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS6_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS6_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* ========================================================  DATBAS7  ======================================================== */
 #define R_I3C0_DATBAS7_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
 #define R_I3C0_DATBAS7_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_DATBAS7_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
 #define R_I3C0_DATBAS7_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS7_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
 #define R_I3C0_DATBAS7_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS7_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
 #define R_I3C0_DATBAS7_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_DATBAS7_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
 #define R_I3C0_DATBAS7_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_DATBAS7_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
 #define R_I3C0_DATBAS7_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_DATBAS7_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
 #define R_I3C0_DATBAS7_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_DATBAS7_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
 #define R_I3C0_DATBAS7_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
/* =======================================================  EXDATBAS  ======================================================== */
 #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
 #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
 #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
 #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
 #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
 #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
 #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
/* =======================================================  SDATBAS0  ======================================================== */
 #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
 #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
 #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
 #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
 #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
 #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
/* =======================================================  SDATBAS1  ======================================================== */
 #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
 #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
 #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
 #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
 #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
 #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
/* =======================================================  SDATBAS2  ======================================================== */
 #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
 #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
 #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
 #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
 #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
 #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
 #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
/* ========================================================  MSDCT0  ========================================================= */
 #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT0_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT0_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT1  ========================================================= */
 #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT1_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT1_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT2  ========================================================= */
 #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT2_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT2_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT3  ========================================================= */
 #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT3_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT3_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT4  ========================================================= */
 #define R_I3C0_MSDCT4_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT4_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT4_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT4_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT4_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT4_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT4_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT4_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT4_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT5  ========================================================= */
 #define R_I3C0_MSDCT5_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT5_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT5_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT5_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT5_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT5_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT5_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT5_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT5_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT6  ========================================================= */
 #define R_I3C0_MSDCT6_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT6_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT6_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT6_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT6_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT6_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT6_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT6_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT6_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* ========================================================  MSDCT7  ========================================================= */
 #define R_I3C0_MSDCT7_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
 #define R_I3C0_MSDCT7_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
 #define R_I3C0_MSDCT7_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
 #define R_I3C0_MSDCT7_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
 #define R_I3C0_MSDCT7_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR4_Pos        (12UL)         /*!< RBCR4 (Bit 12)                                        */
 #define R_I3C0_MSDCT7_RBCR4_Msk        (0x1000UL)     /*!< RBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR5_Pos        (13UL)         /*!< RBCR5 (Bit 13)                                        */
 #define R_I3C0_MSDCT7_RBCR5_Msk        (0x2000UL)     /*!< RBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_MSDCT7_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
 #define R_I3C0_MSDCT7_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
/* =========================================================  SVDCT  ========================================================= */
 #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
 #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
 #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
 #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
 #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
 #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
 #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR4_Pos         (12UL)         /*!< TBCR4 (Bit 12)                                        */
 #define R_I3C0_SVDCT_TBCR4_Msk         (0x1000UL)     /*!< TBCR4 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR5_Pos         (13UL)         /*!< TBCR5 (Bit 13)                                        */
 #define R_I3C0_SVDCT_TBCR5_Msk         (0x2000UL)     /*!< TBCR5 (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
 #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
/* =======================================================  SDCTPIDL  ======================================================== */
/* =======================================================  SDCTPIDH  ======================================================== */
/* ========================================================  SVDVAD0  ======================================================== */
 #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
 #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
 #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
 #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
 #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
 #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
/* ========================================================  SVDVAD1  ======================================================== */
 #define R_I3C0_SVDVAD1_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
 #define R_I3C0_SVDVAD1_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
 #define R_I3C0_SVDVAD1_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
 #define R_I3C0_SVDVAD1_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDVAD1_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
 #define R_I3C0_SVDVAD1_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SVDVAD1_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
 #define R_I3C0_SVDVAD1_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
/* ========================================================  SVDVAD2  ======================================================== */
 #define R_I3C0_SVDVAD2_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
 #define R_I3C0_SVDVAD2_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
 #define R_I3C0_SVDVAD2_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
 #define R_I3C0_SVDVAD2_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_SVDVAD2_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
 #define R_I3C0_SVDVAD2_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_SVDVAD2_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
 #define R_I3C0_SVDVAD2_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
/* ========================================================  CSECMD  ========================================================= */
 #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
 #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
 #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
 #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
/* ========================================================  CEACTST  ======================================================== */
 #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
 #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
/* =========================================================  CMWLG  ========================================================= */
 #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
 #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CMRLG  ========================================================= */
 #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
 #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
 #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
 #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
/* ========================================================  CETSTMD  ======================================================== */
 #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
 #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
/* ========================================================  CGDVST  ========================================================= */
 #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
 #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
 #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
 #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
 #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
 #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
 #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
/* ========================================================  CMDSPW  ========================================================= */
 #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
 #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
/* ========================================================  CMDSPR  ========================================================= */
 #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
 #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
 #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
 #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
/* ========================================================  CMDSPT  ========================================================= */
 #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
 #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
 #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
 #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CETSM  ========================================================= */
 #define R_I3C0_CETSM_SPTSYN_Pos        (0UL)          /*!< SPTSYN (Bit 0)                                        */
 #define R_I3C0_CETSM_SPTSYN_Msk        (0x1UL)        /*!< SPTSYN (Bitfield-Mask: 0x01)                          */
 #define R_I3C0_CETSM_SPTASYN0_Pos      (1UL)          /*!< SPTASYN0 (Bit 1)                                      */
 #define R_I3C0_CETSM_SPTASYN0_Msk      (0x2UL)        /*!< SPTASYN0 (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_CETSM_SPTASYN1_Pos      (2UL)          /*!< SPTASYN1 (Bit 2)                                      */
 #define R_I3C0_CETSM_SPTASYN1_Msk      (0x4UL)        /*!< SPTASYN1 (Bitfield-Mask: 0x01)                        */
 #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
 #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
 #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
 #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
/* =========================================================  CETSS  ========================================================= */
 #define R_I3C0_CETSS_SYNE_Pos          (0UL)          /*!< SYNE (Bit 0)                                          */
 #define R_I3C0_CETSS_SYNE_Msk          (0x1UL)        /*!< SYNE (Bitfield-Mask: 0x01)                            */
 #define R_I3C0_CETSS_ASYNE_Pos         (1UL)          /*!< ASYNE (Bit 1)                                         */
 #define R_I3C0_CETSS_ASYNE_Msk         (0x6UL)        /*!< ASYNE (Bitfield-Mask: 0x03)                           */
 #define R_I3C0_CETSS_ICOVF_Pos         (7UL)          /*!< ICOVF (Bit 7)                                         */
 #define R_I3C0_CETSS_ICOVF_Msk         (0x80UL)       /*!< ICOVF (Bitfield-Mask: 0x01)                           */
/* =======================================================  CGHDRCAP  ======================================================== */
 #define R_I3C0_CGHDRCAP_DDREN_Pos      (0UL)          /*!< DDREN (Bit 0)                                         */
 #define R_I3C0_CGHDRCAP_DDREN_Msk      (0x1UL)        /*!< DDREN (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_CGHDRCAP_TSPEN_Pos      (1UL)          /*!< TSPEN (Bit 1)                                         */
 #define R_I3C0_CGHDRCAP_TSPEN_Msk      (0x2UL)        /*!< TSPEN (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_CGHDRCAP_TSLEN_Pos      (2UL)          /*!< TSLEN (Bit 2)                                         */
 #define R_I3C0_CGHDRCAP_TSLEN_Msk      (0x4UL)        /*!< TSLEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  BITCNT  ========================================================= */
 #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
 #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
 #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
 #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
/* ========================================================  NQSTLV  ========================================================= */
 #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
 #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
 #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
 #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
 #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
 #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
/* =======================================================  NDBSTLV0  ======================================================== */
 #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
 #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
 #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
/* =======================================================  NRSQSTLV  ======================================================== */
 #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
 #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
/* ========================================================  HQSTLV  ========================================================= */
 #define R_I3C0_HQSTLV_CMDQLV_Pos       (0UL)          /*!< CMDQLV (Bit 0)                                        */
 #define R_I3C0_HQSTLV_CMDQLV_Msk       (0xffUL)       /*!< CMDQLV (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_HQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
 #define R_I3C0_HQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
/* ========================================================  HDBSTLV  ======================================================== */
 #define R_I3C0_HDBSTLV_TDBFLV_Pos      (0UL)          /*!< TDBFLV (Bit 0)                                        */
 #define R_I3C0_HDBSTLV_TDBFLV_Msk      (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
 #define R_I3C0_HDBSTLV_RDBLV_Pos       (8UL)          /*!< RDBLV (Bit 8)                                         */
 #define R_I3C0_HDBSTLV_RDBLV_Msk       (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
/* ========================================================  PRSTDBG  ======================================================== */
 #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
 #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
 #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
 #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
 #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
 #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
/* =======================================================  MSERRCNT  ======================================================== */
 #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
 #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
/* ========================================================  SC1CPT  ========================================================= */
 #define R_I3C0_SC1CPT_SC1C_Pos         (0UL)          /*!< SC1C (Bit 0)                                          */
 #define R_I3C0_SC1CPT_SC1C_Msk         (0xffffUL)     /*!< SC1C (Bitfield-Mask: 0xffff)                          */
/* ========================================================  SC2CPT  ========================================================= */
 #define R_I3C0_SC2CPT_SC2C_Pos         (0UL)          /*!< SC2C (Bit 0)                                          */
 #define R_I3C0_SC2CPT_SC2C_Msk         (0xffffUL)     /*!< SC2C (Bitfield-Mask: 0xffff)                          */

/* =========================================================================================================================== */
/* ================                                        R_MPU_MMPU                                         ================ */
/* =========================================================================================================================== */

/* ==========================================================  OAD  ========================================================== */
 #define R_MPU_MMPU_OAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_OAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_OAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
 #define R_MPU_MMPU_OAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
/* =========================================================  OADPT  ========================================================= */
 #define R_MPU_MMPU_OADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_MPU_MMPU_OADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
 #define R_MPU_MMPU_OADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_MPU_MMPU_OADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                        R_MPU_SPMON                                        ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                          R_MSTP                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  MSTPCRA  ======================================================== */
 #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
 #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
/* ========================================================  MSTPCRB  ======================================================== */
 #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
 #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
/* ========================================================  MSTPCRC  ======================================================== */
 #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
 #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
/* ========================================================  MSTPCRD  ======================================================== */
 #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
 #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
/* ========================================================  MSTPCRE  ======================================================== */
 #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
 #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
/* =======================================================  LSMRWDIS  ======================================================== */
 #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
 #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
 #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
 #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
 #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
 #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
 #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
 #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
 #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
 #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */

/* =========================================================================================================================== */
/* ================                                          R_PORT0                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  PCNTR1  ========================================================= */
 #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
 #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
 #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
 #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  PODR  ========================================================== */
 #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
 #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PDR  ========================================================== */
 #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
 #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
/* ========================================================  PCNTR2  ========================================================= */
 #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
 #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
 #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
 #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
/* =========================================================  EIDR  ========================================================== */
 #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
 #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
/* =========================================================  PIDR  ========================================================== */
 #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
 #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
/* ========================================================  PCNTR3  ========================================================= */
 #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
 #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
 #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
 #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
/* =========================================================  PORR  ========================================================== */
 #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
 #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
/* =========================================================  POSR  ========================================================== */
 #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
 #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
/* ========================================================  PCNTR4  ========================================================= */
 #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
 #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
 #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
 #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
/* =========================================================  EORR  ========================================================== */
 #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
 #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
/* =========================================================  EOSR  ========================================================== */
 #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
 #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */

/* =========================================================================================================================== */
/* ================                                           R_PFS                                           ================ */
/* =========================================================================================================================== */

/* =========================================================================================================================== */
/* ================                                          R_PMISC                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  PWPR  ========================================================== */
 #define R_PMISC_PWPR_PFSWE_Pos      (6UL)    /*!< PFSWE (Bit 6)                                         */
 #define R_PMISC_PWPR_PFSWE_Msk      (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
 #define R_PMISC_PWPR_B0WI_Pos       (7UL)    /*!< B0WI (Bit 7)                                          */
 #define R_PMISC_PWPR_B0WI_Msk       (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
/* =========================================================  PWPRS  ========================================================= */
 #define R_PMISC_PWPRS_PFSWE_Pos     (6UL)    /*!< PFSWE (Bit 6)                                         */
 #define R_PMISC_PWPRS_PFSWE_Msk     (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
 #define R_PMISC_PWPRS_B0WI_Pos      (7UL)    /*!< B0WI (Bit 7)                                          */
 #define R_PMISC_PWPRS_B0WI_Msk      (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
/* ========================================================  PRWCNTR  ======================================================== */
 #define R_PMISC_PRWCNTR_WAIT_Pos    (0UL)    /*!< WAIT (Bit 0)                                          */
 #define R_PMISC_PRWCNTR_WAIT_Msk    (0xfUL)  /*!< WAIT (Bitfield-Mask: 0x0f)                            */
/* =========================================================  PSAR  ========================================================== */
 #define R_PMISC_PSAR_PORTSA0_Pos    (0UL)    /*!< PORTSA0 (Bit 0)                                       */
 #define R_PMISC_PSAR_PORTSA0_Msk    (0x1UL)  /*!< PORTSA0 (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                          R_QSPI                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  SFMSMD  ========================================================= */
 #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
 #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
 #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
 #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
 #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
 #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
 #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
 #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
 #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
 #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
 #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
/* ========================================================  SFMSSC  ========================================================= */
 #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
 #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
 #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
 #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
/* ========================================================  SFMSKC  ========================================================= */
 #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
 #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
 #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
/* ========================================================  SFMSST  ========================================================= */
 #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
 #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
 #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
 #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
 #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
 #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
/* ========================================================  SFMCOM  ========================================================= */
 #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
 #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
/* ========================================================  SFMCMD  ========================================================= */
 #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
 #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
/* ========================================================  SFMCST  ========================================================= */
 #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
 #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
 #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
 #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
/* ========================================================  SFMSIC  ========================================================= */
 #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
 #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
/* ========================================================  SFMSAC  ========================================================= */
 #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
 #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
 #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
/* ========================================================  SFMSDC  ========================================================= */
 #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
 #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
 #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
 #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
 #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
 #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
/* ========================================================  SFMSPC  ========================================================= */
 #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
 #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
 #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
 #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
/* ========================================================  SFMPMD  ========================================================= */
 #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
 #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
/* ========================================================  SFMCNT1  ======================================================== */
 #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
 #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */

/* =========================================================================================================================== */
/* ================                                           R_RTC                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  R64CNT  ========================================================= */
 #define R_RTC_R64CNT_R64OVF_Pos      (7UL)      /*!< R64OVF (Bit 7)                                        */
 #define R_RTC_R64CNT_R64OVF_Msk      (0x80UL)   /*!< R64OVF (Bitfield-Mask: 0x01)                          */
 #define R_RTC_R64CNT_FHZ_Pos         (0UL)      /*!< FHZ (Bit 0)                                           */
 #define R_RTC_R64CNT_FHZ_Msk         (0x1UL)    /*!< FHZ (Bitfield-Mask: 0x01)                             */
/* =========================================================  BCNT0  ========================================================= */
 #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
 #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
/* ========================================================  RSECCNT  ======================================================== */
 #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
 #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
 #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  BCNT1  ========================================================= */
 #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
 #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
/* ========================================================  RMINCNT  ======================================================== */
 #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
 #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
 #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  BCNT2  ========================================================= */
 #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
 #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
/* ========================================================  RHRCNT  ========================================================= */
 #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
 #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
 #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
 #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
 #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
 #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
/* =========================================================  BCNT3  ========================================================= */
 #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
 #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
/* ========================================================  RWKCNT  ========================================================= */
 #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
 #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
/* ========================================================  RDAYCNT  ======================================================== */
 #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
 #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
 #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
 #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
/* ========================================================  RMONCNT  ======================================================== */
 #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
 #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
 #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  RYRCNT  ========================================================= */
 #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
 #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
 #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
 #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
/* ========================================================  BCNT0AR  ======================================================== */
 #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
 #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
/* ========================================================  RSECAR  ========================================================= */
 #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
 #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
 #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  BCNT1AR  ======================================================== */
 #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
 #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
/* ========================================================  RMINAR  ========================================================= */
 #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
 #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
 #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
 #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  BCNT2AR  ======================================================== */
 #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
 #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
/* =========================================================  RHRAR  ========================================================= */
 #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
 #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
 #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
 #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
 #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
 #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
/* ========================================================  BCNT3AR  ======================================================== */
 #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
 #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
/* =========================================================  RWKAR  ========================================================= */
 #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
 #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
/* =======================================================  BCNT0AER  ======================================================== */
 #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
 #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
/* ========================================================  RDAYAR  ========================================================= */
 #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
 #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
 #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
 #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
/* =======================================================  BCNT1AER  ======================================================== */
 #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
 #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
/* ========================================================  RMONAR  ========================================================= */
 #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
 #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
 #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
/* =======================================================  BCNT2AER  ======================================================== */
 #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
 #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
/* =========================================================  RYRAR  ========================================================= */
 #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
 #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
 #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
 #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
/* =======================================================  BCNT3AER  ======================================================== */
 #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
 #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
/* ========================================================  RYRAREN  ======================================================== */
 #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
 #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
/* =========================================================  RCR1  ========================================================== */
 #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
 #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
 #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
 #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
 #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
 #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
 #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
 #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
/* =========================================================  RCR2  ========================================================== */
 #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
 #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
 #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
 #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
 #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
 #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
 #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
 #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
 #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
 #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
 #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
/* =========================================================  RCR4  ========================================================== */
 #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
 #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
 #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
 #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
/* =========================================================  RFRH  ========================================================== */
 #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
 #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
/* =========================================================  RFRL  ========================================================== */
 #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
 #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
/* =========================================================  RADJ  ========================================================== */
 #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
 #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
 #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
 #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
/* =========================================================  RADJ2  ========================================================= */
 #define R_RTC_RADJ2_FADJ_Pos         (5UL)      /*!< FADJ (Bit 5)                                          */
 #define R_RTC_RADJ2_FADJ_Msk         (0xffe0UL) /*!< FADJ (Bitfield-Mask: 0x7ff)                           */

/* =========================================================================================================================== */
/* ================                                          R_SCI0                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  SMR  ========================================================== */
 #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
 #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
 #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
 #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
 #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
 #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
 #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
 #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
/* =======================================================  SMR_SMCI  ======================================================== */
 #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
 #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
 #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
 #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
 #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
 #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
 #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
 #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
/* ==========================================================  BRR  ========================================================== */
 #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
 #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  SCR  ========================================================== */
 #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
 #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
 #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
 #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
 #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
 #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
 #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
 #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
/* =======================================================  SCR_SMCI  ======================================================== */
 #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
 #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
 #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
 #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
 #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
 #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
 #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
 #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
/* ==========================================================  TDR  ========================================================== */
 #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
 #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
/* ==========================================================  SSR  ========================================================== */
 #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
 #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
 #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
 #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
 #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
 #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
 #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
 #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
 #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
/* =======================================================  SSR_FIFO  ======================================================== */
 #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
 #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
 #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
 #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
 #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
 #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
 #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
 #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
/* =======================================================  SSR_MANC  ======================================================== */
 #define R_SCI0_SSR_MANC_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
 #define R_SCI0_SSR_MANC_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_MANC_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
 #define R_SCI0_SSR_MANC_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_MANC_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
 #define R_SCI0_SSR_MANC_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_MANC_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
 #define R_SCI0_SSR_MANC_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_MANC_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
 #define R_SCI0_SSR_MANC_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_MANC_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
 #define R_SCI0_SSR_MANC_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_MANC_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
 #define R_SCI0_SSR_MANC_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_MANC_MER_Pos        (0UL)      /*!< MER (Bit 0)                                           */
 #define R_SCI0_SSR_MANC_MER_Msk        (0x1UL)    /*!< MER (Bitfield-Mask: 0x01)                             */
/* =======================================================  SSR_SMCI  ======================================================== */
 #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
 #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
 #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
 #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
 #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
 #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
 #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
 #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
 #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
/* ==========================================================  RDR  ========================================================== */
 #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
 #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
/* =========================================================  SCMR  ========================================================== */
 #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
 #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
 #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
 #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
 #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
 #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  SEMR  ========================================================== */
 #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
 #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
 #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
 #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
 #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
 #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
 #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
 #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
 #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
 #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  SNFR  ========================================================== */
 #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
 #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
/* =========================================================  SIMR1  ========================================================= */
 #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
 #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
 #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
 #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
/* =========================================================  SIMR2  ========================================================= */
 #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
 #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
 #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
 #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
 #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
/* =========================================================  SIMR3  ========================================================= */
 #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
 #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
 #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
 #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
 #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
 #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
 #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
 #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
 #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
 #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
 #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
 #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
/* =========================================================  SISR  ========================================================== */
 #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
 #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
/* =========================================================  SPMR  ========================================================== */
 #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
 #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
 #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
 #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
 #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
 #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
 #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
 #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
/* =========================================================  TDRHL  ========================================================= */
 #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
 #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
/* ========================================================  FTDRHL  ========================================================= */
 #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
 #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
 #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  FTDRH  ========================================================= */
 #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
 #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
 #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
/* =========================================================  FTDRL  ========================================================= */
 #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
 #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
/* =========================================================  RDRHL  ========================================================= */
 #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
 #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
/* ========================================================  FRDRHL  ========================================================= */
 #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
 #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
 #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
 #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
 #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
 #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
 #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
 #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
/* =======================================================  TDRHL_MAN  ======================================================= */
 #define R_SCI0_TDRHL_MAN_TDAT_Pos      (0UL)      /*!< TDAT (Bit 0)                                          */
 #define R_SCI0_TDRHL_MAN_TDAT_Msk      (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
 #define R_SCI0_TDRHL_MAN_MPBT_Pos      (9UL)      /*!< MPBT (Bit 9)                                          */
 #define R_SCI0_TDRHL_MAN_MPBT_Msk      (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_TDRHL_MAN_TSYNC_Pos     (12UL)     /*!< TSYNC (Bit 12)                                        */
 #define R_SCI0_TDRHL_MAN_TSYNC_Msk     (0x1000UL) /*!< TSYNC (Bitfield-Mask: 0x01)                           */
/* =======================================================  RDRHL_MAN  ======================================================= */
 #define R_SCI0_RDRHL_MAN_RDAT_Pos      (0UL)      /*!< RDAT (Bit 0)                                          */
 #define R_SCI0_RDRHL_MAN_RDAT_Msk      (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
 #define R_SCI0_RDRHL_MAN_MPB_Pos       (9UL)      /*!< MPB (Bit 9)                                           */
 #define R_SCI0_RDRHL_MAN_MPB_Msk       (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_RDRHL_MAN_RSYNC_Pos     (12UL)     /*!< RSYNC (Bit 12)                                        */
 #define R_SCI0_RDRHL_MAN_RSYNC_Msk     (0x1000UL) /*!< RSYNC (Bitfield-Mask: 0x01)                           */
/* =========================================================  FRDRH  ========================================================= */
 #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
 #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
 #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
 #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
 #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
 #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
 #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
 #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
 #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
/* =========================================================  FRDRL  ========================================================= */
 #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
 #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
/* =========================================================  MDDR  ========================================================== */
 #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
 #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
/* =========================================================  DCCR  ========================================================== */
 #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
 #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
 #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
 #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
 #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
 #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
/* ==========================================================  FCR  ========================================================== */
 #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
 #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
 #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
 #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
 #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
 #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
 #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
 #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
 #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
 #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
 #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
/* ==========================================================  FDR  ========================================================== */
 #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
 #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
 #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
 #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
/* ==========================================================  LSR  ========================================================== */
 #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
 #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
 #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
 #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
 #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
 #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CDR  ========================================================== */
 #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
 #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
/* =========================================================  SPTR  ========================================================== */
 #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
 #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
 #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
 #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
 #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
 #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
 #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
 #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  ACTR  ========================================================== */
 #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
 #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
 #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
 #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
 #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
 #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
 #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
/* =========================================================  ESMER  ========================================================= */
 #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
 #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR0  ========================================================== */
 #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
 #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
 #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
 #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR1  ========================================================== */
 #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
 #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
 #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
 #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
 #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
 #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
 #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
 #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
/* ==========================================================  CR2  ========================================================== */
 #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
 #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
 #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
 #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
 #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
 #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
/* ==========================================================  CR3  ========================================================== */
 #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
 #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PCR  ========================================================== */
 #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
 #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
 #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
 #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
 #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
 #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
 #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
 #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
 #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
 #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
 #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  STR  ========================================================== */
 #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
 #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
 #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
 #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
 #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
 #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
 #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
/* =========================================================  STCR  ========================================================== */
 #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
 #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
 #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
 #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
 #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
 #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
 #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
/* =========================================================  CF0DR  ========================================================= */
/* =========================================================  CF0CR  ========================================================= */
 #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
 #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
 #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
 #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
 #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
 #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
 #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
 #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
 #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
/* =========================================================  CF0RR  ========================================================= */
/* ========================================================  PCF1DR  ========================================================= */
/* ========================================================  SCF1DR  ========================================================= */
/* =========================================================  CF1CR  ========================================================= */
 #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
 #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
 #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
 #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
 #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
 #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
 #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
 #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
 #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
/* =========================================================  CF1RR  ========================================================= */
/* ==========================================================  TCR  ========================================================== */
 #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
 #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
/* ==========================================================  TMR  ========================================================== */
 #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
 #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
 #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
 #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
 #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
/* =========================================================  TPRE  ========================================================== */
/* =========================================================  TCNT  ========================================================== */
/* =======================================================  SCIMSKEN  ======================================================== */
 #define R_SCI0_SCIMSKEN_MSKEN_Pos      (0UL)    /*!< MSKEN (Bit 0)                                         */
 #define R_SCI0_SCIMSKEN_MSKEN_Msk      (0x1UL)  /*!< MSKEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  MMR  ========================================================== */
 #define R_SCI0_MMR_MANEN_Pos           (7UL)    /*!< MANEN (Bit 7)                                         */
 #define R_SCI0_MMR_MANEN_Msk           (0x80UL) /*!< MANEN (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_MMR_SBSEL_Pos           (6UL)    /*!< SBSEL (Bit 6)                                         */
 #define R_SCI0_MMR_SBSEL_Msk           (0x40UL) /*!< SBSEL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_MMR_SYNSEL_Pos          (5UL)    /*!< SYNSEL (Bit 5)                                        */
 #define R_SCI0_MMR_SYNSEL_Msk          (0x20UL) /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_MMR_SYNVAL_Pos          (4UL)    /*!< SYNVAL (Bit 4)                                        */
 #define R_SCI0_MMR_SYNVAL_Msk          (0x10UL) /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_MMR_ERTEN_Pos           (2UL)    /*!< ERTEN (Bit 2)                                         */
 #define R_SCI0_MMR_ERTEN_Msk           (0x4UL)  /*!< ERTEN (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_MMR_TMPOL_Pos           (1UL)    /*!< TMPOL (Bit 1)                                         */
 #define R_SCI0_MMR_TMPOL_Msk           (0x2UL)  /*!< TMPOL (Bitfield-Mask: 0x01)                           */
 #define R_SCI0_MMR_RMPOL_Pos           (0UL)    /*!< RMPOL (Bit 0)                                         */
 #define R_SCI0_MMR_RMPOL_Msk           (0x1UL)  /*!< RMPOL (Bitfield-Mask: 0x01)                           */
/* =========================================================  TMPR  ========================================================== */
 #define R_SCI0_TMPR_TPLEN_Pos          (0UL)    /*!< TPLEN (Bit 0)                                         */
 #define R_SCI0_TMPR_TPLEN_Msk          (0xfUL)  /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
 #define R_SCI0_TMPR_TPPAT_Pos          (4UL)    /*!< TPPAT (Bit 4)                                         */
 #define R_SCI0_TMPR_TPPAT_Msk          (0x30UL) /*!< TPPAT (Bitfield-Mask: 0x03)                           */
/* =========================================================  RMPR  ========================================================== */
 #define R_SCI0_RMPR_RPLEN_Pos          (0UL)    /*!< RPLEN (Bit 0)                                         */
 #define R_SCI0_RMPR_RPLEN_Msk          (0xfUL)  /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
 #define R_SCI0_RMPR_RPPAT_Pos          (4UL)    /*!< RPPAT (Bit 4)                                         */
 #define R_SCI0_RMPR_RPPAT_Msk          (0x30UL) /*!< RPPAT (Bitfield-Mask: 0x03)                           */
/* =========================================================  MESR  ========================================================== */
 #define R_SCI0_MESR_PFER_Pos           (0UL)    /*!< PFER (Bit 0)                                          */
 #define R_SCI0_MESR_PFER_Msk           (0x1UL)  /*!< PFER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_MESR_SYER_Pos           (1UL)    /*!< SYER (Bit 1)                                          */
 #define R_SCI0_MESR_SYER_Msk           (0x2UL)  /*!< SYER (Bitfield-Mask: 0x01)                            */
 #define R_SCI0_MESR_SBER_Pos           (2UL)    /*!< SBER (Bit 2)                                          */
 #define R_SCI0_MESR_SBER_Msk           (0x4UL)  /*!< SBER (Bitfield-Mask: 0x01)                            */
/* =========================================================  MECR  ========================================================== */
 #define R_SCI0_MECR_PFEREN_Pos         (0UL)    /*!< PFEREN (Bit 0)                                        */
 #define R_SCI0_MECR_PFEREN_Msk         (0x1UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_MECR_SYEREN_Pos         (1UL)    /*!< SYEREN (Bit 1)                                        */
 #define R_SCI0_MECR_SYEREN_Msk         (0x2UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
 #define R_SCI0_MECR_SBEREN_Pos         (2UL)    /*!< SBEREN (Bit 2)                                        */
 #define R_SCI0_MECR_SBEREN_Msk         (0x4UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                          R_SLCDC                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  LCDM0  ========================================================= */
 #define R_SLCDC_LCDM0_MDSET_Pos     (6UL)    /*!< MDSET (Bit 6)                                         */
 #define R_SLCDC_LCDM0_MDSET_Msk     (0xc0UL) /*!< MDSET (Bitfield-Mask: 0x03)                           */
 #define R_SLCDC_LCDM0_LWAVE_Pos     (5UL)    /*!< LWAVE (Bit 5)                                         */
 #define R_SLCDC_LCDM0_LWAVE_Msk     (0x20UL) /*!< LWAVE (Bitfield-Mask: 0x01)                           */
 #define R_SLCDC_LCDM0_LDTY_Pos      (2UL)    /*!< LDTY (Bit 2)                                          */
 #define R_SLCDC_LCDM0_LDTY_Msk      (0x1cUL) /*!< LDTY (Bitfield-Mask: 0x07)                            */
 #define R_SLCDC_LCDM0_LBAS_Pos      (0UL)    /*!< LBAS (Bit 0)                                          */
 #define R_SLCDC_LCDM0_LBAS_Msk      (0x3UL)  /*!< LBAS (Bitfield-Mask: 0x03)                            */
/* =========================================================  LCDM1  ========================================================= */
 #define R_SLCDC_LCDM1_LCDON_Pos     (7UL)    /*!< LCDON (Bit 7)                                         */
 #define R_SLCDC_LCDM1_LCDON_Msk     (0x80UL) /*!< LCDON (Bitfield-Mask: 0x01)                           */
 #define R_SLCDC_LCDM1_SCOC_Pos      (6UL)    /*!< SCOC (Bit 6)                                          */
 #define R_SLCDC_LCDM1_SCOC_Msk      (0x40UL) /*!< SCOC (Bitfield-Mask: 0x01)                            */
 #define R_SLCDC_LCDM1_VLCON_Pos     (5UL)    /*!< VLCON (Bit 5)                                         */
 #define R_SLCDC_LCDM1_VLCON_Msk     (0x20UL) /*!< VLCON (Bitfield-Mask: 0x01)                           */
 #define R_SLCDC_LCDM1_BLON_Pos      (4UL)    /*!< BLON (Bit 4)                                          */
 #define R_SLCDC_LCDM1_BLON_Msk      (0x10UL) /*!< BLON (Bitfield-Mask: 0x01)                            */
 #define R_SLCDC_LCDM1_LCDSEL_Pos    (3UL)    /*!< LCDSEL (Bit 3)                                        */
 #define R_SLCDC_LCDM1_LCDSEL_Msk    (0x8UL)  /*!< LCDSEL (Bitfield-Mask: 0x01)                          */
 #define R_SLCDC_LCDM1_LCDVLM_Pos    (0UL)    /*!< LCDVLM (Bit 0)                                        */
 #define R_SLCDC_LCDM1_LCDVLM_Msk    (0x1UL)  /*!< LCDVLM (Bitfield-Mask: 0x01)                          */
/* =========================================================  LCDC0  ========================================================= */
 #define R_SLCDC_LCDC0_LCDC_Pos      (0UL)    /*!< LCDC (Bit 0)                                          */
 #define R_SLCDC_LCDC0_LCDC_Msk      (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f)                            */
/* =========================================================  VLCD  ========================================================== */
 #define R_SLCDC_VLCD_MDSET2_Pos     (7UL)    /*!< MDSET2 (Bit 7)                                        */
 #define R_SLCDC_VLCD_MDSET2_Msk     (0x80UL) /*!< MDSET2 (Bitfield-Mask: 0x01)                          */
 #define R_SLCDC_VLCD_VLCD_Pos       (0UL)    /*!< VLCD (Bit 0)                                          */
 #define R_SLCDC_VLCD_VLCD_Msk       (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f)                            */
/* ==========================================================  SEG  ========================================================== */
 #define R_SLCDC_SEG_A_Pos           (0UL)    /*!< A (Bit 0)                                             */
 #define R_SLCDC_SEG_A_Msk           (0xfUL)  /*!< A (Bitfield-Mask: 0x0f)                               */
 #define R_SLCDC_SEG_B_Pos           (4UL)    /*!< B (Bit 4)                                             */
 #define R_SLCDC_SEG_B_Msk           (0xf0UL) /*!< B (Bitfield-Mask: 0x0f)                               */

/* =========================================================================================================================== */
/* ================                                          R_SPI0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  SPCR  ========================================================== */
 #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
 #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
 #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
 #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
 #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
 #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
 #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
 #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
 #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
 #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
/* =========================================================  SSLP  ========================================================== */
 #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
 #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
 #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
 #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
 #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
 #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
 #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
 #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
 #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
/* =========================================================  SPPCR  ========================================================= */
 #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
 #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
 #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
 #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
 #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
/* =========================================================  SPSR  ========================================================== */
 #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
 #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
 #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
 #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
 #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
 #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
 #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
 #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
 #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
/* =========================================================  SPDR  ========================================================== */
/* ========================================================  SPDR_HA  ======================================================== */
/* ========================================================  SPDR_BY  ======================================================== */
/* =========================================================  SPSCR  ========================================================= */
 #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
 #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
/* =========================================================  SPBR  ========================================================== */
 #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
 #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
/* =========================================================  SPDCR  ========================================================= */
 #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
 #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
 #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
 #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
 #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
 #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
 #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
/* =========================================================  SPCKD  ========================================================= */
 #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
 #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
/* =========================================================  SSLND  ========================================================= */
 #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
 #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
/* =========================================================  SPND  ========================================================== */
 #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
 #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
/* =========================================================  SPCR2  ========================================================= */
 #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
 #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
 #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
 #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
 #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
 #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
 #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
 #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
/* =========================================================  SPCMD  ========================================================= */
 #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
 #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
 #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
 #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
 #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
 #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
 #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
 #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
 #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
 #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
 #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
 #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
 #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
 #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
/* ========================================================  SPDCR2  ========================================================= */
 #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
 #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
 #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
/* =========================================================  SPSSR  ========================================================= */
 #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
 #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
 #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
 #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
/* =========================================================  SPCR3  ========================================================= */
 #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
 #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
 #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
 #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
 #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
 #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
/* =========================================================  SPPR  ========================================================== */
 #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
 #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
 #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
 #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
 #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
 #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */

/* =========================================================================================================================== */
/* ================                                          R_SRAM                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  PARIOAD  ======================================================== */
 #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
 #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
/* =======================================================  SRAMPRCR  ======================================================== */
 #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
 #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
 #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
 #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
/* =======================================================  SRAMWTSC  ======================================================== */
/* ========================================================  ECCMODE  ======================================================== */
 #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
 #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
/* ========================================================  ECC2STS  ======================================================== */
 #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
 #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
/* =======================================================  ECC1STSEN  ======================================================= */
 #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
 #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
/* ========================================================  ECC1STS  ======================================================== */
 #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
 #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
/* ========================================================  ECCPRCR  ======================================================== */
 #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
 #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
 #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
 #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
/* =======================================================  ECCPRCR2  ======================================================== */
 #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
 #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
 #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
 #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
/* ========================================================  ECCETST  ======================================================== */
 #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
 #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
/* ========================================================  ECCOAD  ========================================================= */
 #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
 #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
/* =======================================================  SRAMPRCR2  ======================================================= */
 #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
 #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
 #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
 #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */

/* =========================================================================================================================== */
/* ================                                          R_SSI0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  SSICR  ========================================================= */
 #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
 #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
 #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
 #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
 #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
 #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
 #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
 #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
 #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
 #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
 #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
 #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
 #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
 #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
 #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
 #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
 #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
 #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
 #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
 #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
 #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
 #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
 #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
 #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
 #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
/* =========================================================  SSISR  ========================================================= */
 #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
 #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
 #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
 #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
 #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
 #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
 #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
 #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
 #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
 #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
 #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
 #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
 #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
 #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
/* ========================================================  SSIFCR  ========================================================= */
 #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
 #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
 #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
 #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
 #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
 #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
 #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
 #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
 #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
 #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
 #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
 #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
 #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
 #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
/* ========================================================  SSIFSR  ========================================================= */
 #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
 #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
 #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
 #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
 #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
 #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
 #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
 #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
/* ========================================================  SSIFTDR  ======================================================== */
 #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
 #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  SSIFTDR16  ======================================================= */
/* =======================================================  SSIFTDR8  ======================================================== */
/* ========================================================  SSIFRDR  ======================================================== */
 #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
 #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  SSIFRDR16  ======================================================= */
/* =======================================================  SSIFRDR8  ======================================================== */
/* ========================================================  SSIOFR  ========================================================= */
 #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
 #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
 #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
 #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
 #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
 #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
/* ========================================================  SSISCR  ========================================================= */
 #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
 #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
 #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
 #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */

/* =========================================================================================================================== */
/* ================                                         R_SYSTEM                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  SBYCR  ========================================================= */
 #define R_SYSTEM_SBYCR_SSBY_Pos                 (15UL)         /*!< SSBY (Bit 15)                                         */
 #define R_SYSTEM_SBYCR_SSBY_Msk                 (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
/* =======================================================  SCKDIVCR  ======================================================== */
 #define R_SYSTEM_SCKDIVCR_FCK_Pos               (28UL)         /*!< FCK (Bit 28)                                          */
 #define R_SYSTEM_SCKDIVCR_FCK_Msk               (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
 #define R_SYSTEM_SCKDIVCR_ICK_Pos               (24UL)         /*!< ICK (Bit 24)                                          */
 #define R_SYSTEM_SCKDIVCR_ICK_Msk               (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
 #define R_SYSTEM_SCKDIVCR_BCK_Pos               (16UL)         /*!< BCK (Bit 16)                                          */
 #define R_SYSTEM_SCKDIVCR_BCK_Msk               (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
 #define R_SYSTEM_SCKDIVCR_PCKA_Pos              (12UL)         /*!< PCKA (Bit 12)                                         */
 #define R_SYSTEM_SCKDIVCR_PCKA_Msk              (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
 #define R_SYSTEM_SCKDIVCR_PCKB_Pos              (8UL)          /*!< PCKB (Bit 8)                                          */
 #define R_SYSTEM_SCKDIVCR_PCKB_Msk              (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
 #define R_SYSTEM_SCKDIVCR_PCKC_Pos              (4UL)          /*!< PCKC (Bit 4)                                          */
 #define R_SYSTEM_SCKDIVCR_PCKC_Msk              (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
 #define R_SYSTEM_SCKDIVCR_PCKD_Pos              (0UL)          /*!< PCKD (Bit 0)                                          */
 #define R_SYSTEM_SCKDIVCR_PCKD_Msk              (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
/* ========================================================  SCKSCR  ========================================================= */
 #define R_SYSTEM_SCKSCR_CKSEL_Pos               (0UL)          /*!< CKSEL (Bit 0)                                         */
 #define R_SYSTEM_SCKSCR_CKSEL_Msk               (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
/* ========================================================  PLLCCR  ========================================================= */
 #define R_SYSTEM_PLLCCR_PLLMUL_Pos              (8UL)          /*!< PLLMUL (Bit 8)                                        */
 #define R_SYSTEM_PLLCCR_PLLMUL_Msk              (0x1f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
 #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos            (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
 #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk            (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_PLLCCR_PLIDIV_Pos              (0UL)          /*!< PLIDIV (Bit 0)                                        */
 #define R_SYSTEM_PLLCCR_PLIDIV_Msk              (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
/* =========================================================  PLLCR  ========================================================= */
 #define R_SYSTEM_PLLCR_PLLSTP_Pos               (0UL)          /*!< PLLSTP (Bit 0)                                        */
 #define R_SYSTEM_PLLCR_PLLSTP_Msk               (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
/* =======================================================  PLLRTCCR  ======================================================== */
 #define R_SYSTEM_PLLRTCCR_PLLRTCSTP_Pos         (0UL)          /*!< PLLRTCSTP (Bit 0)                                     */
 #define R_SYSTEM_PLLRTCCR_PLLRTCSTP_Msk         (0x1UL)        /*!< PLLRTCSTP (Bitfield-Mask: 0x01)                       */
/* ========================================================  MEMWAIT  ======================================================== */
 #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos            (0UL)          /*!< MEMWAIT (Bit 0)                                       */
 #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk            (0x3UL)        /*!< MEMWAIT (Bitfield-Mask: 0x03)                         */
/* ========================================================  MOSCCR  ========================================================= */
 #define R_SYSTEM_MOSCCR_MOSTP_Pos               (0UL)          /*!< MOSTP (Bit 0)                                         */
 #define R_SYSTEM_MOSCCR_MOSTP_Msk               (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
/* ========================================================  HOCOCR  ========================================================= */
 #define R_SYSTEM_HOCOCR_HCSTP_Pos               (0UL)          /*!< HCSTP (Bit 0)                                         */
 #define R_SYSTEM_HOCOCR_HCSTP_Msk               (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
/* ========================================================  MOCOCR  ========================================================= */
 #define R_SYSTEM_MOCOCR_MCSTP_Pos               (0UL)          /*!< MCSTP (Bit 0)                                         */
 #define R_SYSTEM_MOCOCR_MCSTP_Msk               (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
/* =========================================================  OSCSF  ========================================================= */
 #define R_SYSTEM_OSCSF_PLLRTCSF_Pos             (7UL)          /*!< PLLRTCSF (Bit 7)                                      */
 #define R_SYSTEM_OSCSF_PLLRTCSF_Msk             (0x80UL)       /*!< PLLRTCSF (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_OSCSF_PLLSF_Pos                (5UL)          /*!< PLLSF (Bit 5)                                         */
 #define R_SYSTEM_OSCSF_PLLSF_Msk                (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_OSCSF_MOSCSF_Pos               (3UL)          /*!< MOSCSF (Bit 3)                                        */
 #define R_SYSTEM_OSCSF_MOSCSF_Msk               (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_OSCSF_HOCOSF_Pos               (0UL)          /*!< HOCOSF (Bit 0)                                        */
 #define R_SYSTEM_OSCSF_HOCOSF_Msk               (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
/* =========================================================  CKOCR  ========================================================= */
 #define R_SYSTEM_CKOCR_CKOEN_Pos                (7UL)          /*!< CKOEN (Bit 7)                                         */
 #define R_SYSTEM_CKOCR_CKOEN_Msk                (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_CKOCR_CKODIV_Pos               (4UL)          /*!< CKODIV (Bit 4)                                        */
 #define R_SYSTEM_CKOCR_CKODIV_Msk               (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
 #define R_SYSTEM_CKOCR_CKOSEL_Pos               (0UL)          /*!< CKOSEL (Bit 0)                                        */
 #define R_SYSTEM_CKOCR_CKOSEL_Msk               (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
/* ========================================================  OSTDCR  ========================================================= */
 #define R_SYSTEM_OSTDCR_OSTDE_Pos               (7UL)          /*!< OSTDE (Bit 7)                                         */
 #define R_SYSTEM_OSTDCR_OSTDE_Msk               (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_OSTDCR_OSTDIE_Pos              (0UL)          /*!< OSTDIE (Bit 0)                                        */
 #define R_SYSTEM_OSTDCR_OSTDIE_Msk              (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
/* ========================================================  OSTDSR  ========================================================= */
 #define R_SYSTEM_OSTDSR_OSTDF_Pos               (0UL)          /*!< OSTDF (Bit 0)                                         */
 #define R_SYSTEM_OSTDSR_OSTDF_Msk               (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
/* ========================================================  SOSTDCR  ======================================================== */
 #define R_SYSTEM_SOSTDCR_SOSDCE_Pos             (15UL)         /*!< SOSDCE (Bit 15)                                       */
 #define R_SYSTEM_SOSTDCR_SOSDCE_Msk             (0x8000UL)     /*!< SOSDCE (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_SOSTDCR_SOSDCF_Pos             (14UL)         /*!< SOSDCF (Bit 14)                                       */
 #define R_SYSTEM_SOSTDCR_SOSDCF_Msk             (0x4000UL)     /*!< SOSDCF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_SOSTDCR_SOSTDF_Pos             (13UL)         /*!< SOSTDF (Bit 13)                                       */
 #define R_SYSTEM_SOSTDCR_SOSTDF_Msk             (0x2000UL)     /*!< SOSTDF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_SOSTDCR_SOSTDIE_Pos            (12UL)         /*!< SOSTDIE (Bit 12)                                      */
 #define R_SYSTEM_SOSTDCR_SOSTDIE_Msk            (0x1000UL)     /*!< SOSTDIE (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_SOSTDCR_SOSDCCMP_Pos           (0UL)          /*!< SOSDCCMP (Bit 0)                                      */
 #define R_SYSTEM_SOSTDCR_SOSDCCMP_Msk           (0xfffUL)      /*!< SOSDCCMP (Bitfield-Mask: 0xfff)                       */
/* =======================================================  SLCDSCKCR  ======================================================= */
 #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos         (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
 #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk         (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos        (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
 #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk        (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
/* =======================================================  MOCOUTCR  ======================================================== */
 #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos          (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
 #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk          (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
/* =======================================================  HOCOUTCR  ======================================================== */
 #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos          (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
 #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk          (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
/* =========================================================  SNZCR  ========================================================= */
 #define R_SYSTEM_SNZCR_SNZE_Pos                 (7UL)          /*!< SNZE (Bit 7)                                          */
 #define R_SYSTEM_SNZCR_SNZE_Msk                 (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_SNZCR_SNZDTCEN_Pos             (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
 #define R_SYSTEM_SNZCR_SNZDTCEN_Msk             (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SNZCR_RXDREQEN_Pos             (0UL)          /*!< RXDREQEN (Bit 0)                                      */
 #define R_SYSTEM_SNZCR_RXDREQEN_Msk             (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  SNZEDCR  ======================================================== */
 #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos          (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
 #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk          (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
 #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos           (4UL)          /*!< AD0UMTED (Bit 4)                                      */
 #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk           (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SNZEDCR_AD0MATED_Pos           (3UL)          /*!< AD0MATED (Bit 3)                                      */
 #define R_SYSTEM_SNZEDCR_AD0MATED_Msk           (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos           (2UL)          /*!< DTCNZRED (Bit 2)                                      */
 #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk           (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SNZEDCR_DTCZRED_Pos            (1UL)          /*!< DTCZRED (Bit 1)                                       */
 #define R_SYSTEM_SNZEDCR_DTCZRED_Msk            (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos          (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
 #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk          (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
/* =======================================================  SNZEDCR1  ======================================================== */
 #define R_SYSTEM_SNZEDCR1_CTSUNAJED_Pos         (1UL)          /*!< CTSUNAJED (Bit 1)                                     */
 #define R_SYSTEM_SNZEDCR1_CTSUNAJED_Msk         (0x2UL)        /*!< CTSUNAJED (Bitfield-Mask: 0x01)                       */
/* =======================================================  SNZREQCR  ======================================================== */
 #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos        (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk        (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos        (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk        (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos        (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk        (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos        (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk        (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos        (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk        (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos        (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
 #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk        (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos          (0UL)          /*!< SNZREQEN (Bit 0)                                      */
 #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk          (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
/* =========================================================  PSMCR  ========================================================= */
 #define R_SYSTEM_PSMCR_PSMC_Pos                 (0UL)          /*!< PSMC (Bit 0)                                          */
 #define R_SYSTEM_PSMCR_PSMC_Msk                 (0x1UL)        /*!< PSMC (Bitfield-Mask: 0x01)                            */
/* =========================================================  OPCCR  ========================================================= */
 #define R_SYSTEM_OPCCR_OPCMTSF_Pos              (4UL)          /*!< OPCMTSF (Bit 4)                                       */
 #define R_SYSTEM_OPCCR_OPCMTSF_Msk              (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_OPCCR_OPCM_Pos                 (0UL)          /*!< OPCM (Bit 0)                                          */
 #define R_SYSTEM_OPCCR_OPCM_Msk                 (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
/* ========================================================  SOPCCR  ========================================================= */
 #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos            (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
 #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk            (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_SOPCCR_SOPCM_Pos               (0UL)          /*!< SOPCM (Bit 0)                                         */
 #define R_SYSTEM_SOPCCR_SOPCM_Msk               (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
/* =======================================================  MOSCWTCR  ======================================================== */
 #define R_SYSTEM_MOSCWTCR_MSTS_Pos              (0UL)          /*!< MSTS (Bit 0)                                          */
 #define R_SYSTEM_MOSCWTCR_MSTS_Msk              (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
/* ========================================================  SRMPSCR  ======================================================== */
 #define R_SYSTEM_SRMPSCR_SPSC_Pos               (0UL)          /*!< SPSC (Bit 0)                                          */
 #define R_SYSTEM_SRMPSCR_SPSC_Msk               (0x1UL)        /*!< SPSC (Bitfield-Mask: 0x01)                            */
/* ========================================================  RSTSR1  ========================================================= */
 #define R_SYSTEM_RSTSR1_BUSMRF_Pos              (11UL)         /*!< BUSMRF (Bit 11)                                       */
 #define R_SYSTEM_RSTSR1_BUSMRF_Msk              (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_RSTSR1_REERF_Pos               (9UL)          /*!< REERF (Bit 9)                                         */
 #define R_SYSTEM_RSTSR1_REERF_Msk               (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_RSTSR1_RPERF_Pos               (8UL)          /*!< RPERF (Bit 8)                                         */
 #define R_SYSTEM_RSTSR1_RPERF_Msk               (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_RSTSR1_SWRF_Pos                (2UL)          /*!< SWRF (Bit 2)                                          */
 #define R_SYSTEM_RSTSR1_SWRF_Msk                (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_RSTSR1_WDTRF_Pos               (1UL)          /*!< WDTRF (Bit 1)                                         */
 #define R_SYSTEM_RSTSR1_WDTRF_Msk               (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_RSTSR1_IWDTRF_Pos              (0UL)          /*!< IWDTRF (Bit 0)                                        */
 #define R_SYSTEM_RSTSR1_IWDTRF_Msk              (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_RSTSR1_TZERF_Pos               (13UL)         /*!< TZERF (Bit 13)                                        */
 #define R_SYSTEM_RSTSR1_TZERF_Msk               (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_RSTSR1_CPERF_Pos               (15UL)         /*!< CPERF (Bit 15)                                        */
 #define R_SYSTEM_RSTSR1_CPERF_Msk               (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
/* =========================================================  LDOCR  ========================================================= */
 #define R_SYSTEM_LDOCR_CHG0_Pos                 (0UL)          /*!< CHG0 (Bit 0)                                          */
 #define R_SYSTEM_LDOCR_CHG0_Msk                 (0x1UL)        /*!< CHG0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  LVD1CR1  ======================================================== */
 #define R_SYSTEM_LVD1CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
 #define R_SYSTEM_LVD1CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_LVD1CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
 #define R_SYSTEM_LVD1CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
/* ========================================================  LVD2CR1  ======================================================== */
 #define R_SYSTEM_LVD2CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
 #define R_SYSTEM_LVD2CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_LVD2CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
 #define R_SYSTEM_LVD2CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
/* ======================================================  USBCKCR_ALT  ====================================================== */
 #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos      (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
 #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk      (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
/* ========================================================  LVD1SR  ========================================================= */
 #define R_SYSTEM_LVD1SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
 #define R_SYSTEM_LVD1SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
 #define R_SYSTEM_LVD1SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
 #define R_SYSTEM_LVD1SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
/* ========================================================  LVD2SR  ========================================================= */
 #define R_SYSTEM_LVD2SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
 #define R_SYSTEM_LVD2SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
 #define R_SYSTEM_LVD2SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
 #define R_SYSTEM_LVD2SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
/* =========================================================  PRCR  ========================================================== */
 #define R_SYSTEM_PRCR_PRKEY_Pos                 (8UL)          /*!< PRKEY (Bit 8)                                         */
 #define R_SYSTEM_PRCR_PRKEY_Msk                 (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
 #define R_SYSTEM_PRCR_PRC3_Pos                  (3UL)          /*!< PRC3 (Bit 3)                                          */
 #define R_SYSTEM_PRCR_PRC3_Msk                  (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_PRCR_PRC1_Pos                  (1UL)          /*!< PRC1 (Bit 1)                                          */
 #define R_SYSTEM_PRCR_PRC1_Msk                  (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_PRCR_PRC0_Pos                  (0UL)          /*!< PRC0 (Bit 0)                                          */
 #define R_SYSTEM_PRCR_PRC0_Msk                  (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_PRCR_PRC4_Pos                  (4UL)          /*!< PRC4 (Bit 4)                                          */
 #define R_SYSTEM_PRCR_PRC4_Msk                  (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
/* ========================================================  SYOCDCR  ======================================================== */
 #define R_SYSTEM_SYOCDCR_DBGEN_Pos              (7UL)          /*!< DBGEN (Bit 7)                                         */
 #define R_SYSTEM_SYOCDCR_DBGEN_Msk              (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  MOMCR  ========================================================= */
 #define R_SYSTEM_MOMCR_MOSEL_Pos                (6UL)          /*!< MOSEL (Bit 6)                                         */
 #define R_SYSTEM_MOMCR_MOSEL_Msk                (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_MOMCR_MODRV1_Pos               (3UL)          /*!< MODRV1 (Bit 3)                                        */
 #define R_SYSTEM_MOMCR_MODRV1_Msk               (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
/* ========================================================  RSTSR0  ========================================================= */
 #define R_SYSTEM_RSTSR0_LVD2RF_Pos              (3UL)          /*!< LVD2RF (Bit 3)                                        */
 #define R_SYSTEM_RSTSR0_LVD2RF_Msk              (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_RSTSR0_LVD1RF_Pos              (2UL)          /*!< LVD1RF (Bit 2)                                        */
 #define R_SYSTEM_RSTSR0_LVD1RF_Msk              (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_RSTSR0_LVD0RF_Pos              (1UL)          /*!< LVD0RF (Bit 1)                                        */
 #define R_SYSTEM_RSTSR0_LVD0RF_Msk              (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_RSTSR0_PORF_Pos                (0UL)          /*!< PORF (Bit 0)                                          */
 #define R_SYSTEM_RSTSR0_PORF_Msk                (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
/* ========================================================  RSTSR2  ========================================================= */
 #define R_SYSTEM_RSTSR2_CWSF_Pos                (0UL)          /*!< CWSF (Bit 0)                                          */
 #define R_SYSTEM_RSTSR2_CWSF_Msk                (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
/* ========================================================  LVCMPCR  ======================================================== */
 #define R_SYSTEM_LVCMPCR_LVD2E_Pos              (6UL)          /*!< LVD2E (Bit 6)                                         */
 #define R_SYSTEM_LVCMPCR_LVD2E_Msk              (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
 #define R_SYSTEM_LVCMPCR_LVD1E_Pos              (5UL)          /*!< LVD1E (Bit 5)                                         */
 #define R_SYSTEM_LVCMPCR_LVD1E_Msk              (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
/* =======================================================  LVD1CMPCR  ======================================================= */
 #define R_SYSTEM_LVD1CMPCR_LVDLVL_Pos           (0UL)          /*!< LVDLVL (Bit 0)                                        */
 #define R_SYSTEM_LVD1CMPCR_LVDLVL_Msk           (0xfUL)        /*!< LVDLVL (Bitfield-Mask: 0x0f)                          */
 #define R_SYSTEM_LVD1CMPCR_LVDE_Pos             (7UL)          /*!< LVDE (Bit 7)                                          */
 #define R_SYSTEM_LVD1CMPCR_LVDE_Msk             (0x80UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
/* =======================================================  LVD2CMPCR  ======================================================= */
 #define R_SYSTEM_LVD2CMPCR_LVDLVL_Pos           (0UL)          /*!< LVDLVL (Bit 0)                                        */
 #define R_SYSTEM_LVD2CMPCR_LVDLVL_Msk           (0x7UL)        /*!< LVDLVL (Bitfield-Mask: 0x07)                          */
 #define R_SYSTEM_LVD2CMPCR_EXVCCINP2_Pos        (6UL)          /*!< EXVCCINP2 (Bit 6)                                     */
 #define R_SYSTEM_LVD2CMPCR_EXVCCINP2_Msk        (0x40UL)       /*!< EXVCCINP2 (Bitfield-Mask: 0x01)                       */
 #define R_SYSTEM_LVD2CMPCR_LVDE_Pos             (7UL)          /*!< LVDE (Bit 7)                                          */
 #define R_SYSTEM_LVD2CMPCR_LVDE_Msk             (0x80UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
/* ========================================================  LVD1CR0  ======================================================== */
 #define R_SYSTEM_LVD1CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
 #define R_SYSTEM_LVD1CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_LVD1CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
 #define R_SYSTEM_LVD1CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_LVD1CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
 #define R_SYSTEM_LVD1CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_LVD1CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
 #define R_SYSTEM_LVD1CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
/* ========================================================  LVD2CR0  ======================================================== */
 #define R_SYSTEM_LVD2CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
 #define R_SYSTEM_LVD2CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_LVD2CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
 #define R_SYSTEM_LVD2CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_LVD2CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
 #define R_SYSTEM_LVD2CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_LVD2CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
 #define R_SYSTEM_LVD2CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
/* ========================================================  SOSCCR  ========================================================= */
 #define R_SYSTEM_SOSCCR_SOSTP_Pos               (0UL)          /*!< SOSTP (Bit 0)                                         */
 #define R_SYSTEM_SOSCCR_SOSTP_Msk               (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
/* =========================================================  SOMCR  ========================================================= */
 #define R_SYSTEM_SOMCR_SODRV_Pos                (0UL)          /*!< SODRV (Bit 0)                                         */
 #define R_SYSTEM_SOMCR_SODRV_Msk                (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
 #define R_SYSTEM_SOMCR_EXCLKS_Pos               (4UL)          /*!< EXCLKS (Bit 4)                                        */
 #define R_SYSTEM_SOMCR_EXCLKS_Msk               (0x10UL)       /*!< EXCLKS (Bitfield-Mask: 0x01)                          */
/* =========================================================  SOMRG  ========================================================= */
 #define R_SYSTEM_SOMRG_SOSCMRG_Pos              (0UL)          /*!< SOSCMRG (Bit 0)                                       */
 #define R_SYSTEM_SOMRG_SOSCMRG_Msk              (0x3UL)        /*!< SOSCMRG (Bitfield-Mask: 0x03)                         */
/* ========================================================  LOCOCR  ========================================================= */
 #define R_SYSTEM_LOCOCR_LCSTP_Pos               (0UL)          /*!< LCSTP (Bit 0)                                         */
 #define R_SYSTEM_LOCOCR_LCSTP_Msk               (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
/* =======================================================  LOCOUTCR  ======================================================== */
 #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos          (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
 #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk          (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
/* ========================================================  PLL2CR  ========================================================= */
 #define R_SYSTEM_PLL2CR_PLL2STP_Pos             (0UL)          /*!< PLL2STP (Bit 0)                                       */
 #define R_SYSTEM_PLL2CR_PLL2STP_Msk             (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
/* =====================================================  CANFDCKDIVCR  ====================================================== */
 #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos    (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
 #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk    (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
/* ======================================================  I3CCKDIVCR  ======================================================= */
 #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos        (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
 #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk        (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
/* ========================================================  USBCKCR  ======================================================== */
 #define R_SYSTEM_USBCKCR_USBCKSEL_Pos           (0UL)          /*!< USBCKSEL (Bit 0)                                      */
 #define R_SYSTEM_USBCKCR_USBCKSEL_Msk           (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
 #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos          (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
 #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk          (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
 #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos          (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
 #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk          (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
/* =======================================================  CANFDCKCR  ======================================================= */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos       (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk       (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos      (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk      (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos      (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
 #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk      (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
/* ========================================================  I3CCKCR  ======================================================== */
 #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos           (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
 #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk           (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
 #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos          (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
 #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk          (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
 #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos          (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
 #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk          (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
/* ========================================================  CGFSAR  ========================================================= */
 #define R_SYSTEM_CGFSAR_NONSEC00_Pos            (0UL)          /*!< NONSEC00 (Bit 0)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC00_Msk            (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC02_Pos            (2UL)          /*!< NONSEC02 (Bit 2)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC02_Msk            (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC03_Pos            (3UL)          /*!< NONSEC03 (Bit 3)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC03_Msk            (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC04_Pos            (4UL)          /*!< NONSEC04 (Bit 4)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC04_Msk            (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC05_Pos            (5UL)          /*!< NONSEC05 (Bit 5)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC05_Msk            (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC06_Pos            (6UL)          /*!< NONSEC06 (Bit 6)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC06_Msk            (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC07_Pos            (7UL)          /*!< NONSEC07 (Bit 7)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC07_Msk            (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC08_Pos            (8UL)          /*!< NONSEC08 (Bit 8)                                      */
 #define R_SYSTEM_CGFSAR_NONSEC08_Msk            (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC11_Pos            (11UL)         /*!< NONSEC11 (Bit 11)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC11_Msk            (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC20_Pos            (20UL)         /*!< NONSEC20 (Bit 20)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC20_Msk            (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC26_Pos            (26UL)         /*!< NONSEC26 (Bit 26)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC26_Msk            (0x4000000UL)  /*!< NONSEC26 (Bitfield-Mask: 0x01)                        */
 #define R_SYSTEM_CGFSAR_NONSEC27_Pos            (27UL)         /*!< NONSEC27 (Bit 27)                                     */
 #define R_SYSTEM_CGFSAR_NONSEC27_Msk            (0x8000000UL)  /*!< NONSEC27 (Bitfield-Mask: 0x01)                        */
/* ========================================================  LPMSAR  ========================================================= */
 #define R_SYSTEM_LPMSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
 #define R_SYSTEM_LPMSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LPMSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
 #define R_SYSTEM_LPMSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LPMSAR_NONSEC4_Pos             (4UL)          /*!< NONSEC4 (Bit 4)                                       */
 #define R_SYSTEM_LPMSAR_NONSEC4_Msk             (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
/* ========================================================  LVDSAR  ========================================================= */
 #define R_SYSTEM_LVDSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
 #define R_SYSTEM_LVDSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LVDSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
 #define R_SYSTEM_LVDSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LVDSAR_NONSEC8_Pos             (8UL)          /*!< NONSEC8 (Bit 8)                                       */
 #define R_SYSTEM_LVDSAR_NONSEC8_Msk             (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LVDSAR_NONSEC9_Pos             (9UL)          /*!< NONSEC9 (Bit 9)                                       */
 #define R_SYSTEM_LVDSAR_NONSEC9_Msk             (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_LVDSAR_NONSEC10_Pos            (10UL)         /*!< NONSEC10 (Bit 10)                                     */
 #define R_SYSTEM_LVDSAR_NONSEC10_Msk            (0x400UL)      /*!< NONSEC10 (Bitfield-Mask: 0x01)                        */
/* ========================================================  RSTSAR  ========================================================= */
 #define R_SYSTEM_RSTSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
 #define R_SYSTEM_RSTSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_RSTSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
 #define R_SYSTEM_RSTSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
 #define R_SYSTEM_RSTSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
 #define R_SYSTEM_RSTSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
/* =======================================================  VBTLVDCR  ======================================================== */
 #define R_SYSTEM_VBTLVDCR_LVDE_Pos              (4UL)          /*!< LVDE (Bit 4)                                          */
 #define R_SYSTEM_VBTLVDCR_LVDE_Msk              (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_VBTLVDCR_LVL_Pos               (5UL)          /*!< LVL (Bit 5)                                           */
 #define R_SYSTEM_VBTLVDCR_LVL_Msk               (0xe0UL)       /*!< LVL (Bitfield-Mask: 0x07)                             */
/* =======================================================  VBTLVDSR  ======================================================== */
 #define R_SYSTEM_VBTLVDSR_DET_Pos               (1UL)          /*!< DET (Bit 1)                                           */
 #define R_SYSTEM_VBTLVDSR_DET_Msk               (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
 #define R_SYSTEM_VBTLVDSR_MON_Pos               (5UL)          /*!< MON (Bit 5)                                           */
 #define R_SYSTEM_VBTLVDSR_MON_Msk               (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
/* =======================================================  VBTCMPCR  ======================================================== */
 #define R_SYSTEM_VBTCMPCR_CMPE_Pos              (0UL)          /*!< CMPE (Bit 0)                                          */
 #define R_SYSTEM_VBTCMPCR_CMPE_Msk              (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
/* =======================================================  VBTLVDICR  ======================================================= */
 #define R_SYSTEM_VBTLVDICR_IE_Pos               (0UL)          /*!< IE (Bit 0)                                            */
 #define R_SYSTEM_VBTLVDICR_IE_Msk               (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_VBTLVDICR_IDTSEL_Pos           (4UL)          /*!< IDTSEL (Bit 4)                                        */
 #define R_SYSTEM_VBTLVDICR_IDTSEL_Msk           (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
/* =======================================================  VRTLVDCR  ======================================================== */
 #define R_SYSTEM_VRTLVDCR_LVDE_Pos              (4UL)          /*!< LVDE (Bit 4)                                          */
 #define R_SYSTEM_VRTLVDCR_LVDE_Msk              (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
 #define R_SYSTEM_VRTLVDCR_LVL_Pos               (5UL)          /*!< LVL (Bit 5)                                           */
 #define R_SYSTEM_VRTLVDCR_LVL_Msk               (0xe0UL)       /*!< LVL (Bitfield-Mask: 0x07)                             */
/* =========================================================  VRTSR  ========================================================= */
 #define R_SYSTEM_VRTSR_PORDET_Pos               (0UL)          /*!< PORDET (Bit 0)                                        */
 #define R_SYSTEM_VRTSR_PORDET_Msk               (0x1UL)        /*!< PORDET (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_VRTSR_DET_Pos                  (1UL)          /*!< DET (Bit 1)                                           */
 #define R_SYSTEM_VRTSR_DET_Msk                  (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
 #define R_SYSTEM_VRTSR_VRTVLD_Pos               (4UL)          /*!< VRTVLD (Bit 4)                                        */
 #define R_SYSTEM_VRTSR_VRTVLD_Msk               (0x10UL)       /*!< VRTVLD (Bitfield-Mask: 0x01)                          */
 #define R_SYSTEM_VRTSR_MON_Pos                  (5UL)          /*!< MON (Bit 5)                                           */
 #define R_SYSTEM_VRTSR_MON_Msk                  (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
/* =======================================================  VRTCMPCR  ======================================================== */
 #define R_SYSTEM_VRTCMPCR_CMPE_Pos              (0UL)          /*!< CMPE (Bit 0)                                          */
 #define R_SYSTEM_VRTCMPCR_CMPE_Msk              (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
/* =======================================================  VRTLVDICR  ======================================================= */
 #define R_SYSTEM_VRTLVDICR_IE_Pos               (0UL)          /*!< IE (Bit 0)                                            */
 #define R_SYSTEM_VRTLVDICR_IE_Msk               (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_VRTLVDICR_IDTSEL_Pos           (4UL)          /*!< IDTSEL (Bit 4)                                        */
 #define R_SYSTEM_VRTLVDICR_IDTSEL_Msk           (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
/* ========================================================  EXLVDCR  ======================================================== */
 #define R_SYSTEM_EXLVDCR_LVDE_Pos               (4UL)          /*!< LVDE (Bit 4)                                          */
 #define R_SYSTEM_EXLVDCR_LVDE_Msk               (0x10UL)       /*!< LVDE (Bitfield-Mask: 0x01)                            */
/* ========================================================  EXLVDSR  ======================================================== */
 #define R_SYSTEM_EXLVDSR_DET_Pos                (1UL)          /*!< DET (Bit 1)                                           */
 #define R_SYSTEM_EXLVDSR_DET_Msk                (0x2UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
 #define R_SYSTEM_EXLVDSR_MON_Pos                (5UL)          /*!< MON (Bit 5)                                           */
 #define R_SYSTEM_EXLVDSR_MON_Msk                (0x20UL)       /*!< MON (Bitfield-Mask: 0x01)                             */
/* ======================================================  EXLVDCMPCR  ======================================================= */
 #define R_SYSTEM_EXLVDCMPCR_CMPE_Pos            (0UL)          /*!< CMPE (Bit 0)                                          */
 #define R_SYSTEM_EXLVDCMPCR_CMPE_Msk            (0x1UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
/* =======================================================  EXLVDICR  ======================================================== */
 #define R_SYSTEM_EXLVDICR_IE_Pos                (0UL)          /*!< IE (Bit 0)                                            */
 #define R_SYSTEM_EXLVDICR_IE_Msk                (0x1UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
 #define R_SYSTEM_EXLVDICR_IDTSEL_Pos            (4UL)          /*!< IDTSEL (Bit 4)                                        */
 #define R_SYSTEM_EXLVDICR_IDTSEL_Msk            (0x30UL)       /*!< IDTSEL (Bitfield-Mask: 0x03)                          */

/* =========================================================================================================================== */
/* ================                                           R_TSN                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  TSCDR  ========================================================= */
/* ========================================================  TSCDRH  ========================================================= */
 #define R_TSN_TSCDRH_TSCDRH_Pos    (0UL)    /*!< TSCDRH (Bit 0)                                        */
 #define R_TSN_TSCDRH_TSCDRH_Msk    (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff)                          */
/* ========================================================  TSCDRL  ========================================================= */
 #define R_TSN_TSCDRL_TSCDRL_Pos    (0UL)    /*!< TSCDRL (Bit 0)                                        */
 #define R_TSN_TSCDRL_TSCDRL_Msk    (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff)                          */
/* ========================================================  TSCDRR  ========================================================= */

/* =========================================================================================================================== */
/* ================                                         R_USB_FS0                                         ================ */
/* =========================================================================================================================== */

/* ========================================================  SYSCFG  ========================================================= */
 #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
 #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
 #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
 #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
 #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
 #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
 #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
 #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
/* ========================================================  BUSWAIT  ======================================================== */
 #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
 #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
/* ========================================================  SYSSTS0  ======================================================== */
 #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
 #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
 #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
 #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
 #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
 #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
 #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
/* ========================================================  PLLSTA  ========================================================= */
 #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
 #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
/* =======================================================  DVSTCTR0  ======================================================== */
 #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
 #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
 #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
 #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
 #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
 #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
 #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
 #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
 #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
 #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
/* =======================================================  TESTMODE  ======================================================== */
 #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
 #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
/* ========================================================  CFIFOL  ========================================================= */
/* ========================================================  CFIFOLL  ======================================================== */
/* =========================================================  CFIFO  ========================================================= */
/* ========================================================  CFIFOH  ========================================================= */
/* ========================================================  CFIFOHH  ======================================================== */
/* ========================================================  D0FIFOL  ======================================================== */
/* =======================================================  D0FIFOLL  ======================================================== */
/* ========================================================  D0FIFO  ========================================================= */
/* ========================================================  D0FIFOH  ======================================================== */
/* =======================================================  D0FIFOHH  ======================================================== */
/* ========================================================  D1FIFOL  ======================================================== */
/* =======================================================  D1FIFOLL  ======================================================== */
/* ========================================================  D1FIFO  ========================================================= */
/* ========================================================  D1FIFOH  ======================================================== */
/* =======================================================  D1FIFOHH  ======================================================== */
/* =======================================================  CFIFOSEL  ======================================================== */
 #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
 #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
 #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
 #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
 #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
 #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
 #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
 #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
/* =======================================================  CFIFOCTR  ======================================================== */
 #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
 #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
 #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
 #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
 #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
/* =======================================================  D0FIFOSEL  ======================================================= */
 #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
 #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
 #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
 #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
 #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
 #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
 #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
 #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
 #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
/* =======================================================  D0FIFOCTR  ======================================================= */
 #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
 #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
 #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
 #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
 #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
/* =======================================================  D1FIFOSEL  ======================================================= */
 #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
 #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
 #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
 #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
 #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
 #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
 #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
 #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
 #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
/* =======================================================  D1FIFOCTR  ======================================================= */
 #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
 #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
 #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
 #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
 #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
/* ========================================================  INTENB0  ======================================================== */
 #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
 #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
 #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
 #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
 #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
 #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
 #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
 #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
 #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTENB1  ======================================================== */
 #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
 #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
 #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
 #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
 #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
 #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
 #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
 #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
 #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
/* ========================================================  BRDYENB  ======================================================== */
 #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
 #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
/* ========================================================  NRDYENB  ======================================================== */
 #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
 #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
/* ========================================================  BEMPENB  ======================================================== */
 #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
 #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
/* ========================================================  SOFCFG  ========================================================= */
 #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
 #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
 #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
 #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
 #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
/* ========================================================  PHYSET  ========================================================= */
 #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
 #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
 #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
 #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
 #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
 #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
 #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
 #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
 #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
 #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTSTS0  ======================================================== */
 #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
 #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
 #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
 #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
 #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
 #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
 #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
 #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
 #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
 #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
 #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
 #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
 #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
 #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
/* ========================================================  INTSTS1  ======================================================== */
 #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
 #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
 #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
 #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
 #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
 #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
 #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
 #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
 #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
 #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
 #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
/* ========================================================  BRDYSTS  ======================================================== */
 #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
 #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
/* ========================================================  NRDYSTS  ======================================================== */
 #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
 #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
/* ========================================================  BEMPSTS  ======================================================== */
 #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
 #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
/* ========================================================  FRMNUM  ========================================================= */
 #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
 #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
 #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
 #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
/* ========================================================  DVCHGR  ========================================================= */
 #define R_USB_FS0_DVCHGR_DVCHG_Pos             (15UL)       /*!< DVCHG (Bit 15)                                        */
 #define R_USB_FS0_DVCHGR_DVCHG_Msk             (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
/* ========================================================  USBADDR  ======================================================== */
 #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
 #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0xf00UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x0f)                       */
 #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
 #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
/* ========================================================  USBREQ  ========================================================= */
 #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
 #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
 #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
 #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
/* ========================================================  USBVAL  ========================================================= */
 #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
 #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
/* ========================================================  USBINDX  ======================================================== */
 #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
 #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
/* ========================================================  USBLENG  ======================================================== */
 #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
 #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
/* ========================================================  DCPCFG  ========================================================= */
 #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
 #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
 #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
 #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
/* ========================================================  DCPMAXP  ======================================================== */
 #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
 #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
 #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
 #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
/* ========================================================  DCPCTR  ========================================================= */
 #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
 #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
 #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
 #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
 #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
 #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
 #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
 #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
 #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
 #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
/* ========================================================  PIPESEL  ======================================================== */
 #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
 #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PIPECFG  ======================================================== */
 #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
 #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
 #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
 #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
 #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
 #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
 #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
 #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
/* =======================================================  PIPEMAXP  ======================================================== */
 #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
 #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
 #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
 #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
/* =======================================================  PIPEPERI  ======================================================== */
 #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
 #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
 #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
/* =======================================================  PIPE_CTR  ======================================================== */
 #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
 #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
 #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
 #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
 #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
 #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
 #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
 #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
 #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
 #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
 #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
 #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
/* ========================================================  DEVADD  ========================================================= */
 #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
 #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
 #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
 #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
 #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
 #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
/* ======================================================  USBBCCTRL0  ======================================================= */
 #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
 #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
 #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
 #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
 #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
 #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
 #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
 #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
 #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
 #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
 #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  UCKSEL  ========================================================= */
 #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
 #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
/* =========================================================  USBMC  ========================================================= */
 #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
 #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
 #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
/* ========================================================  PHYSLEW  ======================================================== */
 #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
 #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
 #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
 #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
 #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
/* ========================================================  LPCTRL  ========================================================= */
 #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
 #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
/* =========================================================  LPSTS  ========================================================= */
 #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
 #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
/* ========================================================  BCCTRL  ========================================================= */
 #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
 #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
 #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
 #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
 #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
 #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
 #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
 #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
 #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
/* =======================================================  PL1CTRL1  ======================================================== */
 #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
 #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
 #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
 #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
 #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
 #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
 #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
 #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
 #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
 #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
/* =======================================================  PL1CTRL2  ======================================================== */
 #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
 #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
 #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
/* =======================================================  HL1CTRL1  ======================================================== */
 #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
 #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
 #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
 #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
/* =======================================================  HL1CTRL2  ======================================================== */
 #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
 #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
 #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
 #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
 #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
 #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
 #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
/* ========================================================  DPUSR0R  ======================================================== */
 #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
 #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
 #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
 #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
/* ========================================================  DPUSR1R  ======================================================== */
 #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
 #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
 #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
 #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
 #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
 #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
 #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
/* ========================================================  DPUSR2R  ======================================================== */
 #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
 #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
 #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
 #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
 #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
 #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
 #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
/* ========================================================  DPUSRCR  ======================================================== */
 #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
 #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
 #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
/* ======================================================  DPUSR0R_FS  ======================================================= */
 #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
 #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
 #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
 #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
 #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
 #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
 #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
 #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
 #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
 #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
 #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
 #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
/* ======================================================  DPUSR1R_FS  ======================================================= */
 #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
 #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
 #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
 #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
 #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
 #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
 #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
 #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
 #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
 #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
 #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */

/* =========================================================================================================================== */
/* ================                                         R_UARTA0                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  TXBAn  ========================================================= */
/* =========================================================  RXBAn  ========================================================= */
/* ========================================================  ASIMAn0  ======================================================== */
 #define R_UARTA0_ASIMAn0_ISRMA_Pos    (0UL)    /*!< ISRMA (Bit 0)                                         */
 #define R_UARTA0_ASIMAn0_ISRMA_Msk    (0x1UL)  /*!< ISRMA (Bitfield-Mask: 0x01)                           */
 #define R_UARTA0_ASIMAn0_ISSMA_Pos    (1UL)    /*!< ISSMA (Bit 1)                                         */
 #define R_UARTA0_ASIMAn0_ISSMA_Msk    (0x2UL)  /*!< ISSMA (Bitfield-Mask: 0x01)                           */
 #define R_UARTA0_ASIMAn0_RXEA_Pos     (5UL)    /*!< RXEA (Bit 5)                                          */
 #define R_UARTA0_ASIMAn0_RXEA_Msk     (0x20UL) /*!< RXEA (Bitfield-Mask: 0x01)                            */
 #define R_UARTA0_ASIMAn0_TXEA_Pos     (6UL)    /*!< TXEA (Bit 6)                                          */
 #define R_UARTA0_ASIMAn0_TXEA_Msk     (0x40UL) /*!< TXEA (Bitfield-Mask: 0x01)                            */
 #define R_UARTA0_ASIMAn0_EN_Pos       (7UL)    /*!< EN (Bit 7)                                            */
 #define R_UARTA0_ASIMAn0_EN_Msk       (0x80UL) /*!< EN (Bitfield-Mask: 0x01)                              */
/* ========================================================  ASIMAn1  ======================================================== */
 #define R_UARTA0_ASIMAn1_ALV_Pos      (0UL)    /*!< ALV (Bit 0)                                           */
 #define R_UARTA0_ASIMAn1_ALV_Msk      (0x1UL)  /*!< ALV (Bitfield-Mask: 0x01)                             */
 #define R_UARTA0_ASIMAn1_DIR_Pos      (1UL)    /*!< DIR (Bit 1)                                           */
 #define R_UARTA0_ASIMAn1_DIR_Msk      (0x2UL)  /*!< DIR (Bitfield-Mask: 0x01)                             */
 #define R_UARTA0_ASIMAn1_SL_Pos       (2UL)    /*!< SL (Bit 2)                                            */
 #define R_UARTA0_ASIMAn1_SL_Msk       (0x4UL)  /*!< SL (Bitfield-Mask: 0x01)                              */
 #define R_UARTA0_ASIMAn1_CL_Pos       (3UL)    /*!< CL (Bit 3)                                            */
 #define R_UARTA0_ASIMAn1_CL_Msk       (0x18UL) /*!< CL (Bitfield-Mask: 0x03)                              */
 #define R_UARTA0_ASIMAn1_PS_Pos       (5UL)    /*!< PS (Bit 5)                                            */
 #define R_UARTA0_ASIMAn1_PS_Msk       (0x60UL) /*!< PS (Bitfield-Mask: 0x03)                              */
/* ========================================================  BRGCAn  ========================================================= */
/* ========================================================  ASISAn  ========================================================= */
 #define R_UARTA0_ASISAn_OVEA_Pos      (0UL)    /*!< OVEA (Bit 0)                                          */
 #define R_UARTA0_ASISAn_OVEA_Msk      (0x1UL)  /*!< OVEA (Bitfield-Mask: 0x01)                            */
 #define R_UARTA0_ASISAn_FEA_Pos       (1UL)    /*!< FEA (Bit 1)                                           */
 #define R_UARTA0_ASISAn_FEA_Msk       (0x2UL)  /*!< FEA (Bitfield-Mask: 0x01)                             */
 #define R_UARTA0_ASISAn_PEA_Pos       (2UL)    /*!< PEA (Bit 2)                                           */
 #define R_UARTA0_ASISAn_PEA_Msk       (0x4UL)  /*!< PEA (Bitfield-Mask: 0x01)                             */
 #define R_UARTA0_ASISAn_TXSFA_Pos     (4UL)    /*!< TXSFA (Bit 4)                                         */
 #define R_UARTA0_ASISAn_TXSFA_Msk     (0x10UL) /*!< TXSFA (Bitfield-Mask: 0x01)                           */
 #define R_UARTA0_ASISAn_TXBFA_Pos     (5UL)    /*!< TXBFA (Bit 5)                                         */
 #define R_UARTA0_ASISAn_TXBFA_Msk     (0x20UL) /*!< TXBFA (Bitfield-Mask: 0x01)                           */
/* ========================================================  ASCTAn  ========================================================= */
 #define R_UARTA0_ASCTAn_OVECTA_Pos    (0UL)    /*!< OVECTA (Bit 0)                                        */
 #define R_UARTA0_ASCTAn_OVECTA_Msk    (0x1UL)  /*!< OVECTA (Bitfield-Mask: 0x01)                          */
 #define R_UARTA0_ASCTAn_FECTA_Pos     (1UL)    /*!< FECTA (Bit 1)                                         */
 #define R_UARTA0_ASCTAn_FECTA_Msk     (0x2UL)  /*!< FECTA (Bitfield-Mask: 0x01)                           */
 #define R_UARTA0_ASCTAn_PECTA_Pos     (2UL)    /*!< PECTA (Bit 2)                                         */
 #define R_UARTA0_ASCTAn_PECTA_Msk     (0x4UL)  /*!< PECTA (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                        R_UARTA_CK                                         ================ */
/* =========================================================================================================================== */

/* ========================================================  UTAnCK  ========================================================= */
 #define R_UARTA_CK_UTAnCK_CK_Pos     (0UL)    /*!< CK (Bit 0)                                            */
 #define R_UARTA_CK_UTAnCK_CK_Msk     (0xfUL)  /*!< CK (Bitfield-Mask: 0x0f)                              */
 #define R_UARTA_CK_UTAnCK_SEL_Pos    (4UL)    /*!< SEL (Bit 4)                                           */
 #define R_UARTA_CK_UTAnCK_SEL_Msk    (0x30UL) /*!< SEL (Bitfield-Mask: 0x03)                             */
 #define R_UARTA_CK_UTAnCK_EN_Pos     (7UL)    /*!< EN (Bit 7)                                            */
 #define R_UARTA_CK_UTAnCK_EN_Msk     (0x80UL) /*!< EN (Bitfield-Mask: 0x01)                              */

/* =========================================================================================================================== */
/* ================                                           R_WDT                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  WDTRR  ========================================================= */
 #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
 #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
/* =========================================================  WDTCR  ========================================================= */
 #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
 #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
 #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
 #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
 #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
 #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
 #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
 #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
/* =========================================================  WDTSR  ========================================================= */
 #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
 #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
 #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
 #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
 #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
 #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
/* ========================================================  WDTRCR  ========================================================= */
 #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
 #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
/* =======================================================  WDTCSTPR  ======================================================== */
 #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
 #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */

/* =========================================================================================================================== */
/* ================                                           R_TZF                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  TZFOAD  ========================================================= */
 #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
 #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
 #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
/* =========================================================  TZFPT  ========================================================= */
 #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
 #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
 #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
 #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */

/* =========================================================================================================================== */
/* ================                                          R_CACHE                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  CCACTL  ========================================================= */
 #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
 #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
/* ========================================================  CCAFCT  ========================================================= */
 #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
 #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
/* ========================================================  CCALCF  ========================================================= */
 #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
 #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
/* ========================================================  SCACTL  ========================================================= */
 #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
 #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
/* ========================================================  SCAFCT  ========================================================= */
 #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
 #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
/* ========================================================  SCALCF  ========================================================= */
 #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
 #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
/* ========================================================  CAPOAD  ========================================================= */
 #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
 #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
/* ========================================================  CAPRCR  ========================================================= */
 #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
 #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
 #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
 #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */

/* =========================================================================================================================== */
/* ================                                          R_CPSCU                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  CSAR  ========================================================== */
 #define R_CPSCU_CSAR_CACHESA_Pos              (0UL)          /*!< CACHESA (Bit 0)                                       */
 #define R_CPSCU_CSAR_CACHESA_Msk              (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
 #define R_CPSCU_CSAR_CACHELSA_Pos             (1UL)          /*!< CACHELSA (Bit 1)                                      */
 #define R_CPSCU_CSAR_CACHELSA_Msk             (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
 #define R_CPSCU_CSAR_CACHEESA_Pos             (2UL)          /*!< CACHEESA (Bit 2)                                      */
 #define R_CPSCU_CSAR_CACHEESA_Msk             (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
/* ========================================================  SRAMSAR  ======================================================== */
 #define R_CPSCU_SRAMSAR_SRAMSA0_Pos           (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
 #define R_CPSCU_SRAMSAR_SRAMSA0_Msk           (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
 #define R_CPSCU_SRAMSAR_SRAMSA1_Pos           (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
 #define R_CPSCU_SRAMSAR_SRAMSA1_Msk           (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
 #define R_CPSCU_SRAMSAR_SRAMSA2_Pos           (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
 #define R_CPSCU_SRAMSAR_SRAMSA2_Msk           (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
/* =======================================================  STBRAMSAR  ======================================================= */
 #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos         (0UL)          /*!< NSBSTBR (Bit 0)                                       */
 #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk         (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
/* ========================================================  DTCSAR  ========================================================= */
 #define R_CPSCU_DTCSAR_DTCSTSA_Pos            (0UL)          /*!< DTCSTSA (Bit 0)                                       */
 #define R_CPSCU_DTCSAR_DTCSTSA_Msk            (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
/* ========================================================  DMACSAR  ======================================================== */
 #define R_CPSCU_DMACSAR_DMASTSA_Pos           (0UL)          /*!< DMASTSA (Bit 0)                                       */
 #define R_CPSCU_DMACSAR_DMASTSA_Msk           (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
/* ========================================================  ICUSARA  ======================================================== */
 #define R_CPSCU_ICUSARA_SAIRQCRn_Pos          (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
 #define R_CPSCU_ICUSARA_SAIRQCRn_Msk          (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
/* ========================================================  ICUSARB  ======================================================== */
 #define R_CPSCU_ICUSARB_SANMI_Pos             (0UL)          /*!< SANMI (Bit 0)                                         */
 #define R_CPSCU_ICUSARB_SANMI_Msk             (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
/* ========================================================  ICUSARC  ======================================================== */
 #define R_CPSCU_ICUSARC_SADMACn_Pos           (0UL)          /*!< SADMACn (Bit 0)                                       */
 #define R_CPSCU_ICUSARC_SADMACn_Msk           (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
/* ========================================================  ICUSARD  ======================================================== */
 #define R_CPSCU_ICUSARD_SASELSR0_Pos          (0UL)          /*!< SASELSR0 (Bit 0)                                      */
 #define R_CPSCU_ICUSARD_SASELSR0_Msk          (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
/* ========================================================  ICUSARE  ======================================================== */
 #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos         (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
 #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk         (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
 #define R_CPSCU_ICUSARE_SALVD1WUP_Pos         (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
 #define R_CPSCU_ICUSARE_SALVD1WUP_Msk         (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
 #define R_CPSCU_ICUSARE_SALVD2WUP_Pos         (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
 #define R_CPSCU_ICUSARE_SALVD2WUP_Msk         (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
 #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos        (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
 #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk        (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Pos      (23UL)         /*!< SAACMPLP0WUP (Bit 23)                                 */
 #define R_CPSCU_ICUSARE_SAACMPLP0WUP_Msk      (0x800000UL)   /*!< SAACMPLP0WUP (Bitfield-Mask: 0x01)                    */
 #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos       (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
 #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk       (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos       (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
 #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk       (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos       (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
 #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk       (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos       (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
 #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk       (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos       (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
 #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk       (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos       (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
 #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk       (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos         (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
 #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk         (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
/* ========================================================  ICUSARF  ======================================================== */
 #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos       (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
 #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk       (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos       (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
 #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk       (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos       (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
 #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk       (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos      (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
 #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk      (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
 #define R_CPSCU_ICUSARF_SASOSCWUP_Pos         (7UL)          /*!< SASOSCWUP (Bit 7)                                     */
 #define R_CPSCU_ICUSARF_SASOSCWUP_Msk         (0x80UL)       /*!< SASOSCWUP (Bitfield-Mask: 0x01)                       */
 #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos        (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
 #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk        (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos        (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
 #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk        (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos        (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
 #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk        (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARF_SAI3CWUP_Pos          (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
 #define R_CPSCU_ICUSARF_SAI3CWUP_Msk          (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
 #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos        (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
 #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk        (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos        (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
 #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk        (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
 #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos        (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
 #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk        (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
/* ========================================================  ICUSARG  ======================================================== */
 #define R_CPSCU_ICUSARG_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
 #define R_CPSCU_ICUSARG_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  ICUSARH  ======================================================== */
 #define R_CPSCU_ICUSARH_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
 #define R_CPSCU_ICUSARH_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  ICUSARI  ======================================================== */
 #define R_CPSCU_ICUSARI_SAIELSRn_Pos          (0UL)          /*!< SAIELSRn (Bit 0)                                      */
 #define R_CPSCU_ICUSARI_SAIELSRn_Msk          (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  ICUSARM  ======================================================== */
 #define R_CPSCU_ICUSARM_SAINTUR0WUP_Pos       (0UL)          /*!< SAINTUR0WUP (Bit 0)                                   */
 #define R_CPSCU_ICUSARM_SAINTUR0WUP_Msk       (0x1UL)        /*!< SAINTUR0WUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARM_SAINTURE0WUP_Pos      (1UL)          /*!< SAINTURE0WUP (Bit 1)                                  */
 #define R_CPSCU_ICUSARM_SAINTURE0WUP_Msk      (0x2UL)        /*!< SAINTURE0WUP (Bitfield-Mask: 0x01)                    */
 #define R_CPSCU_ICUSARM_SAINTUR1WUP_Pos       (2UL)          /*!< SAINTUR1WUP (Bit 2)                                   */
 #define R_CPSCU_ICUSARM_SAINTUR1WUP_Msk       (0x4UL)        /*!< SAINTUR1WUP (Bitfield-Mask: 0x01)                     */
 #define R_CPSCU_ICUSARM_SAINTURE1WUP_Pos      (3UL)          /*!< SAINTURE1WUP (Bit 3)                                  */
 #define R_CPSCU_ICUSARM_SAINTURE1WUP_Msk      (0x8UL)        /*!< SAINTURE1WUP (Bitfield-Mask: 0x01)                    */
 #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Pos    (4UL)          /*!< SAEXLVDVBATWUP (Bit 4)                                */
 #define R_CPSCU_ICUSARM_SAEXLVDVBATWUP_Msk    (0x10UL)       /*!< SAEXLVDVBATWUP (Bitfield-Mask: 0x01)                  */
 #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Pos      (5UL)          /*!< SALVDVRTCWUP (Bit 5)                                  */
 #define R_CPSCU_ICUSARM_SALVDVRTCWUP_Msk      (0x20UL)       /*!< SALVDVRTCWUP (Bitfield-Mask: 0x01)                    */
 #define R_CPSCU_ICUSARM_SAEXLVDWUP_Pos        (6UL)          /*!< SAEXLVDWUP (Bit 6)                                    */
 #define R_CPSCU_ICUSARM_SAEXLVDWUP_Msk        (0x40UL)       /*!< SAEXLVDWUP (Bitfield-Mask: 0x01)                      */
/* ========================================================  BUSSARA  ======================================================== */
 #define R_CPSCU_BUSSARA_BUSSA0_Pos            (0UL)          /*!< BUSSA0 (Bit 0)                                        */
 #define R_CPSCU_BUSSARA_BUSSA0_Msk            (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  BUSSARB  ======================================================== */
 #define R_CPSCU_BUSSARB_BUSSB0_Pos            (0UL)          /*!< BUSSB0 (Bit 0)                                        */
 #define R_CPSCU_BUSSARB_BUSSB0_Msk            (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  BUSSARC  ======================================================== */
 #define R_CPSCU_BUSSARC_BUSSC0_Pos            (0UL)          /*!< BUSSC0 (Bit 0)                                        */
 #define R_CPSCU_BUSSARC_BUSSC0_Msk            (0x1UL)        /*!< BUSSC0 (Bitfield-Mask: 0x01)                          */
/* ========================================================  BUSPARC  ======================================================== */
 #define R_CPSCU_BUSPARC_BUSPA0_Pos            (0UL)          /*!< BUSPA0 (Bit 0)                                        */
 #define R_CPSCU_BUSPARC_BUSPA0_Msk            (0x1UL)        /*!< BUSPA0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  MMPUSARA  ======================================================== */
 #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos         (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
 #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk         (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
/* =======================================================  MMPUSARB  ======================================================== */
 #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos         (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
 #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk         (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
/* ========================================================  TZFSAR  ========================================================= */
 #define R_CPSCU_TZFSAR_TZFSA0_Pos             (0UL)          /*!< TZFSA0 (Bit 0)                                        */
 #define R_CPSCU_TZFSAR_TZFSA0_Msk             (0x1UL)        /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  DEBUGSAR  ======================================================== */
 #define R_CPSCU_DEBUGSAR_DBGSA0_Pos           (0UL)          /*!< DBGSA0 (Bit 0)                                        */
 #define R_CPSCU_DEBUGSAR_DBGSA0_Msk           (0x1UL)        /*!< DBGSA0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  DMACCHSAR  ======================================================= */
 #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos      (0UL)          /*!< DMACCHSARn (Bit 0)                                    */
 #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk      (0xffUL)       /*!< DMACCHSARn (Bitfield-Mask: 0xff)                      */
/* ========================================================  CPUDSAR  ======================================================== */
 #define R_CPSCU_CPUDSAR_CPUDSA0_Pos           (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
 #define R_CPSCU_CPUDSAR_CPUDSA0_Msk           (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
/* ======================================================  SRAMSABAR0  ======================================================= */
 #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos      (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
 #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk      (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
/* ======================================================  SRAMSABAR1  ======================================================= */
 #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos      (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
 #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk      (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
/* ========================================================  TEVTRCR  ======================================================== */
 #define R_CPSCU_TEVTRCR_TEVTE_Pos             (0UL)          /*!< TEVTE (Bit 0)                                         */
 #define R_CPSCU_TEVTRCR_TEVTE_Msk             (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */

/* =========================================================================================================================== */
/* ================                                          R_DOC_B                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  DOCR  ========================================================== */
 #define R_DOC_B_DOCR_OMS_Pos         (0UL)    /*!< OMS (Bit 0)                                           */
 #define R_DOC_B_DOCR_OMS_Msk         (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
 #define R_DOC_B_DOCR_DOBW_Pos        (3UL)    /*!< DOBW (Bit 3)                                          */
 #define R_DOC_B_DOCR_DOBW_Msk        (0x8UL)  /*!< DOBW (Bitfield-Mask: 0x01)                            */
 #define R_DOC_B_DOCR_DCSEL_Pos       (4UL)    /*!< DCSEL (Bit 4)                                         */
 #define R_DOC_B_DOCR_DCSEL_Msk       (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07)                           */
/* =========================================================  DOSR  ========================================================== */
 #define R_DOC_B_DOSR_DOPCF_Pos       (0UL)    /*!< DOPCF (Bit 0)                                         */
 #define R_DOC_B_DOSR_DOPCF_Msk       (0x1UL)  /*!< DOPCF (Bitfield-Mask: 0x01)                           */
/* =========================================================  DOSCR  ========================================================= */
 #define R_DOC_B_DOSCR_DOPCFCL_Pos    (0UL)    /*!< DOPCFCL (Bit 0)                                       */
 #define R_DOC_B_DOSCR_DOPCFCL_Msk    (0x1UL)  /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
/* =========================================================  DODIR  ========================================================= */
/* ========================================================  DODSR0  ========================================================= */
/* ========================================================  DODSR1  ========================================================= */

/* =========================================================================================================================== */
/* ================                                          R_AGTX0                                          ================ */
/* =========================================================================================================================== */

/** @} */ /* End of group PosMask_peripherals */

 #ifdef __cplusplus
}
 #endif

#endif                                 /* R7FA4L1BD_H */

/** @} */ /* End of group R7FA4L1BD */

/** @} */ /* End of group Renesas Electronics Corporation */
